AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
ID
683856
Date
9/24/2018
Public
1.1. Reference Design Overview
1.2. Getting Started
1.3. Reference Design Components
1.4. Compiling the Reference Design
1.5. Testing the Reference Design
1.6. Extending the Reference Design with Custom Persona
1.7. Document Revision History for AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.5.2. fpga-configure
Use the fpga-configure utility to perform partial reconfiguration. The script accepts a .rbf file for a given persona. The script performs the following functions:
- Communicates with the driver to remove device sub-drivers, if any
- Communicates with the fpga-region-controller script to assert/de-assert freeze
- Writes the .rbf to the Partial Reconfiguration Controller IP core
- Re-deploys the sub-drivers, if any, that are required upon successful PR
fpga-configure -p <path-to-rbf> <region_controller_addr>
Option | Description |
---|---|
-p | Performs partial reconfiguration over PCIe* programming. |
-d | Disables the advanced error reporting on the PCIe* link. Advanced error reporting generally reports any critical errors along the PCIe* link, directly to the kernel. If the PCIe* link is completely disabled, the kernel responds by crashing the system. You must disable advanced error reporting during full chip configuration, as full chip configuration brings down the PCIe* link. |
-e | Enables the advanced error reporting for the PCIe* link. Use this option after full chip configuration to ensure the integrity of the PCIe* link. |
-r | Prints the contents of a debug ROM within the reference design. Use for debug purposes. |