External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683842
Date 3/29/2021

2.1. Synthesis Example Design

The synthesis example design contains the major blocks shown in the figure below.
  • A traffic generator, which is a synthesizable Avalon® -MM example driver that implements a pseudo-random pattern of reads and writes to a parameterized number of addresses. The traffic generator also monitors the data read from the memory to ensure it matches the written data and asserts a failure otherwise.
  • An instance of the memory interface, which includes:
    • A memory controller that moderates between the Avalon® -MM interface and the AFI interface.
    • The PHY, which serves as an interface between the memory controller and external memory devices to perform read and write operations.
Figure 5. Synthesis Example Design

If you are using the Ping Pong PHY feature, the synthesis example design includes two traffic generators issuing commands to two independent memory devices through two independent controllers and a common PHY, as shown in the following figure.

Figure 6. Synthesis Example Design for Ping Pong PHY

If you are using RLDRAM 3, the traffic generator in the synthesis example design communicates directly with the PHY using AFI, as shown in the following figure.

Figure 7. Synthesis Example Design for RLDRAM 3 Interfaces

Note: If one or more of the PLL Sharing Mode, DLL Sharing Mode, or OCT Sharing Mode parameters are set to any value other than No Sharing, the synthesis example design will contain two traffic generator/memory interface instances. The two traffic generator/memory interface instances are related only by shared PLL/DLL/OCT connections as defined by the parameter settings. The traffic generator/memory interface instances demonstrate how you can make such connections in your own designs.
Note: Third-party synthesis flow as described in Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis is not a supported flow for EMIF IP.