External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683842
Date 3/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Arria® 10 FPGA IP 2. Design Example Description for External Memory Interfaces Intel® Arria® 10 FPGA IP 3. Document Revision History for External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Arria® 10 FPGA IP x
1.1. Creating an EMIF Project 1.2. Generating and Configuring the EMIF IP 1.3. Generating the Synthesizable EMIF Design Example 1.4. Generating the EMIF Design Example for Simulation 1.5. Simulation Versus Hardware Implementation 1.6. Simulating External Memory Interface IP With ModelSim 1.7. Pin Placement for Intel® Arria® 10 EMIF IP 1.8. Compiling and Programming the Intel® Arria® 10 EMIF Design Example 1.9. Debugging the Intel® Arria® 10 EMIF Design Example
1.2. Generating and Configuring the EMIF IP x
1.2.1. Intel® Arria® 10 EMIF Parameter Editor Guidelines
2. Design Example Description for External Memory Interfaces Intel® Arria® 10 FPGA IP x
2.1. Synthesis Example Design 2.2. Simulation Example Design 2.3. Example Designs Interface Tab
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Arria® 10 FPGA IP
2. Design Example Description for External Memory Interfaces Intel® Arria® 10 FPGA IP
3. Document Revision History for External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide

1.9. Debugging the Intel® Arria® 10 EMIF Design Example

The EMIF Debug Toolkit is available to assist in debugging external memory interface designs. The toolkit allows you to display read and write margins and generate eye diagrams. After you have programmed the Intel® Arria® 10 development kit, you can verify its operation using the EMIF Debug Toolkit.
  1. To launch the EMIF Debug Toolkit, navigate to Tools > System Debugging Tools > External Memory Interface Toolkit.
  2. Click Initialize Connections.
  3. Click Link Project to device. A window appears; verify that the correct device is selected and that the correct .sof file is selected.
  4. Click Create Memory Interface Connection. Accept the default settings by clicking OK.
The Intel® Arria® 10 development kit is now set up to function with the EMIF Debug Toolkit, and you can generate any of the following reports by double-clicking on the corresponding option:
  • Rerun calibration. Produces a calibration report summarizing the calibration status per DQ/DQS group along with the margins for each DQ/DQS pin.
  • Driver Margining. Produces a report summarizing the read and write margins per I/O pin. This differs from calibration margining because driver margining is captured during user mode traffic rather than during calibration
  • Generate Eye Diagram. Generates read and write eye diagrams for each DQ pin based on calibration data patterns.
  • Calibrate Termination. Sweeps different termination values and reports the margins that each termination value provides. Use this feature to help select the optimal termination for the memory interface.

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