Compiled Hardware Accelerator image implemented in FPGA logic that accelerates an application.
|AFU||Accelerator Functional Unit||
Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance.
|API||Application Programming Interface||A set of subroutine definitions, protocols, and tools for building software applications.|
|CCI-P||Core Cache Interface||
CCI-P is the standard interface AFUs use to communicate with the host.
|DFH||Device Feature Header||Creates a linked list of feature headers to provide an extensible way of adding features.|
|FIM||FPGA Interface Manager||
The FPGA hardware containing the FPGA Interface Unit (FIU) and external interfaces for memory, networking, etc.
The Accelerator Function (AF) interfaces with the FIM at run time.
|FIU||FPGA Interface Unit||
FIU is a platform interface layer that acts as a bridge between platform interfaces like PCIe* , UPI and AFU-side interfaces such as CCI-P.
|MPF||Memory Properties Factory||The MPF is a Basic Building Block (BBB) that AFUs can use to provide CCI-P traffic shaping operations for transactions with the FIU.|
|BBBs||Intel® Basic Building Block|| Intel® FPGA Basic Building Blocks are defined as components that can be interfaced with the CCI-P bridge.
For more information, refer to the Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs web page.
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