Streaming DMA Accelerator Functional Unit User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683840
Date 3/06/2020
Public

3.1. Streaming DMA AFU Memory Map

The streaming DMA register map provides the absolute addresses of all the locations within the unit. These registers are in the host view because only the host can access them.
Table 4.  Streaming DMA AFU Memory Map
Byte Address Register Name Span in Bytes Description
0x0000 Streaming DMA AFU DFH 0x40 Device feature header for the streaming DMA AFU. This DFH points to 0x100 as the next DFH offset.
0x0040 2:1 Multiplexer 0x8 Routes the streaming data from either the pattern generator or the Decimator to the S2M BBB.
0x0048 Streaming Decimator 0x8

Performs loopback testing that programmatically filters out

streaming data.

0x0050 1:2 De-multiplexer 0x8 Routes the streaming data to pattern checker and generator or perform loopback testing between the M2S and S2M DMAs.
0x0100 M2S DMA BBB 0x100 Memory-to-stream DMA BBB. The M2S DMA BBB points to 0x100 as the next DFH offset.
0x0200 S2M DMA BBB 0x100 Stream-to-memory DMA BBB. The S2M DMA BBB DFH points to 0x100 as the next DFH offset.
0x0300 NULL DFH 0x40 Null device feature header terminating the DFH linked list.
0x1000 Pattern Checker Memory Slave 0x1000 Pattern checker memory populated by the host application.
0x2000 Pattern Generator Memory Slave 0x1000 Pattern generator memory populated by the host application
0x3000 Pattern Checker CSR Slave 0x10 Pattern checker control and status registers
0x3010 Pattern Generator CSR Slave 0x10 Pattern generator control and status registers.
Figure 5. Streaming DMA AFU Memory Views

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