eCPRI Intel® FPGA IP Design Example User Guide

ID 683837
Date 10/01/2021
Public

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2.5. Design Example Register Map

Below is the register mapping for the eCPRI IP core design example:
Table 6.   eCPRI Intel® FPGA IP Design Example Register Mapping
Address Register
0x20100000 – 0x201FFFFF 2 IOPLL Re-configuration Register.
0x20200000 – 0x203FFFFF Ethernet MAC Avalon-MM Register
0x20400000 – 0x205FFFFF Ethernet MAC Native PHY Avalon-MM Register
0x20600000 – 0x207FFFFF2 Native PHY RS-FEC Avalon-MM Register.
0x40000000 – 0x5FFFFFFF eCPRI IP Avalon-MM Register
0x80000000 – 0x9FFFFFFF Ethernet Design Test Generator/Verifier Avalon-MM Register
Table 7.   Nios® II Register Mapping The registers in below table are only available in the design example generated for Intel® Stratix® 10 or Intel® Agilex™ E-tile devices.
Address Register
0x00100000 – 0x001FFFFF IOPLL Re-configuration Register
0x00200000 – 0x003FFFFF Ethernet MAC Avalon-MM Register
0x00400000 – 0x005FFFFF Ethernet MAC Native PHY Avalon-MM Register
0x00600000 – 0x007FFFFF Native PHY RS-FEC Avalon-MM Register
Note: You can access the Ethernet MAC and Ethernet MAC Native PHY AVMM registers using word offset instead of byte offset.
For detailed information on Ethernet MAC, Ethernet MAC Native PHY, and eCPRI IP core register maps, refer to the respective user guides.
Table 8.   eCPRI Intel® FPGA IP Hardware Design Example Register Map
Word Offset Register Type Default Value Access Type
0x0 Start Send Data:
  • Bit 1: PTP, non-PTP type
  • Bit 0: eCPRI type
0x0 RW
0x1 Continuous Packet Enable 0x0 RW
0x2 Clear Error 0x0 RW
0x3 3 Rate Switch:
  • Bit [7]- Indicates tile:
    • 1'b0: H-tile
    • 1'b1: E-tile
  • Bit [6:4]- Indicates Ethernet data rate switching:
    • 3'b000: 25G to 10G
    • 3'b001: 10G to 25G
  • Bit [0]- Switch rate enable. It's required to set this bit 0 and poll until bit 0 is clear for the rate switching.
Note: This register is not available for Intel® Agilex™ F-tile and Intel® Arria® 10 designs.
  • E-tile: 0x80
  • H-tile: 0x0
RW
0x43 Rate Switch Done:
  • Bit [1] indicates rate switching done.
0x0 RO
0x5 4 System Configuration Status:
  • Bit [31]: System ready
  • Bit [30]: IWF_EN
  • Bit [29]: STARTUP_SEQ_EN
  • Bit [28:4]: Reserved
  • Bit [3]: EXT_PACKET_EN
  • Bit [2:0]: Reserved
0x0 RO
0x64 CPRI Negotiation Complete:
  • Bit [3:0]: Bit rate complete
  • Bit [19:16]: Protocol complete
0x0 RW
0x74 CPRI Negotiation Complete:
  • Bit [3:0]: Fast C&M complete
  • Bit [19:16]: Fast VSS complete
0x0 RW
0x8 - 0x1F Reserved.
0x20 eCPRI Error Interrupt:
  • Bit [0] indicates the interrupt.
0x0 RO
0x21 External Packets Error 0x0 RO
0x22 External PTP Packets TX Start of Packet (SOP) Count 0x0 RO
0x23 External PTP Packets TX End of Packet (EOP) Count 0x0 RO
0x24 External Miscellaneous Packets TX SOP Count 0x0 RO
0x25 External Miscellaneous Packets TX EOP Count 0x0 RO
0x26 External RX Packets SOP Count 0x0 RO
0x27 External RX Packets EOP Count 0x0 RO
0x28 External Packets Error Count 0x0 RO
0x29 - 0x2C Reserved.
0x2D External PTP Timestamp Fingerprint Error Count 0x0 RO
0x2E External PTP Timestamp Fingerprint Error 0x0 RO
0x2F External Rx Error Status 0x0 RO
0x30 - 0x47 Reserved.
0x48 eCPRI Packets Error   RO
0x49 eCPRI TX SOP Count   RO
0x4A eCPRI TX EOP Count   RO
0x4B eCPRI RX SOP Count   RO
0x4C eCPRI RX EOP Count   RO
0x4D eCPRI Packets Error Count   RO
2 Only available in design example generated for Intel® Stratix® 10 and Intel® Agilex™ E-tile devices.
3 Only available in Intel® Stratix® 10 and Intel® Agilex™ designs.
4 Only present in eCPRI design example with IWF feature enabled.

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