1. Quick Start Guide
|Intel® Quartus® Prime Design Suite 21.2|
|IP Version 1.3.1|
The enhanced Common Public Radio Interface (eCPRI) Intel® FPGA IP core implements the eCPRI specification version 2.0. The eCPRI Intel® FPGA IP provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design example in hardware.
- Intel® Agilex™ F-Series Transceiver-SoC Development Kit
- Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit for the H-tile design examples
- Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit for the E-tile design examples
- Intel® Arria® 10 GX Transceiver Signal Integrity Development Kit
The testbench and design example supports 25G and 10G data rates for Intel® Stratix® 10 H-tile or E-tile and Intel® Agilex™ E-tile or F-tile device variations of the eCPRI IP.
- Internal TX to RX serial loopback mode
- Traffic generator and checker
- Basic packet checking capabilities
- Ability to use System Console to run the design and reset the design for re-testing purpose
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