OpenCL* on Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA Quick Start User Guide

ID 683831
Date 6/05/2020

1.3. Acronyms

Table 3.  Acronyms





Accelerator Functional Unit

Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance.


Accelerator Function

Compiled Hardware Accelerator image implemented in FPGA logic that accelerates an application.


Application Programming Interface

A set of subroutine definitions, protocols, and tools for building software applications.


FPGA Interface Manager

The FPGA hardware containing the FPGA Interface Unit (FIU) and external interfaces for memory, networking, etc.

The Accelerator Function (AF) interfaces with the FIM at run time.


Open Programmable Acceleration Engine

The OPAE is a software framework for managing and accessing AFs. 

RoT Root of Trust A source that can be trusted, such as the BMC in the Intel® PAC.
BSP Board Support Package A typical Intel® PAC BSP consists of software layers and a hardware project created using the Intel® Quartus® Prime Pro Edition software that Intel® FPGA SDK for OpenCL* compiler stitches accelerator code into and compiles. The BSP resides in the AFU.