OpenCL* on Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA Quick Start User Guide

Download PDF
ID 683831
Date 6/05/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Setting Up the Host Machine 3. Running Diagnostics 4. OpenCL* Support for Multi-Card Systems 5. Running Samples 6. Compiling OpenCL* Kernels 7. Intel® PAC with Intel® Arria® 10 GX FPGA Security for OpenCL* Applications 8. OpenCL* on the Intel® PAC with Intel® Arria® 10 GX FPGA Quick Start User Guide Archives 9. Document Revision History for OpenCL* Quick Start User Guide Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
1. About this Document x
1.1. Conventions 1.2. Acceleration Glossary 1.3. Acronyms
2. Setting Up the Host Machine x
2.1. Introduction 2.2. Initializing the Environment for OpenCL* with Intel Acceleration Stack 2.3. Initializing the Intel® Acceleration Stack for OpenCL* in a Virtualized Environment
2.1. Introduction x
2.1.1. Release Content
5. Running Samples x
5.1. Running Hello World 5.2. Running Vector Add
6. Compiling OpenCL* Kernels x
6.1. Checking Timing Results
1. About this Document
2. Setting Up the Host Machine
3. Running Diagnostics
4. OpenCL* Support for Multi-Card Systems
5. Running Samples
6. Compiling OpenCL* Kernels
7. Intel® PAC with Intel® Arria® 10 GX FPGA Security for OpenCL* Applications
8. OpenCL* on the Intel® PAC with Intel® Arria® 10 GX FPGA Quick Start User Guide Archives
9. Document Revision History for OpenCL* Quick Start User Guide Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

2.3. Initializing the Intel® Acceleration Stack for OpenCL* in a Virtualized Environment

Follow the installation instructions from the Quick Start Guide to set up the Intel® PAC with Intel® Arria® 10 GX FPGA Intel® FPGA PAC D5005.

Once the stack setup is complete, follow the steps below to setup OpenCL on Intel® FPGA PAC D5005.

You can run the OPAE software in a non-virtualized environment with the Single Root I/O Virtualization (SR-IOV) disabled or in a virtualized environment with the SR-IOV enabled.

To run the OpenCL* reference design in a virtualized environment that includes SR-IOV, follow steps 1 to 3 from section Initializing the Environment for OpenCL with Intel Acceleration Stack and then complete the following additional steps:
  1. Program the required OpenCL* configuration from the host machine by typing the following command:
    aocl program <device name> <filename>

    Sample Output:
    $ aocl program acl0 signed_vector_add.aocx 
aocl program: Running program from /home/DCPsupport/intelrtestack/a10_gx_pac_ias_1_2_1_pv/opencl/opencl_bsp/linux64/libexec
Program succeed.
    You can see the device name in the output for aocl diagnose and you can use one of the pre-compiled bitstream for programming. For example, 
    aocl program acl0 $OPAE_PLATFORM_ROOT/opencl/hello_world.aocx
    Note: The 1.2.1 Release does not allow partial reconfiguration in virtualized environment.
    Note: The 2.0.1 Release does not support partial reconfiguration in virtualized environment.
  2. Enable virtualization using the instructions from section Updating Settings Required for VFs and section Configuring the VF Port on the Host of the Quick Start Guide.
  3. Set the CL_CONTEXT_COMPILER_MODE_INTELFPGA environment variable in the virtual machine to disable FPGA configuration or reconfiguration during OpenCL* host runtime:
    $ export CL_CONTEXT_COMPILER_MODE_INTELFPGA=3
  4. Run the required application from the virtual machine.
  5. Disable virtualization using the instruction from section Disconnecting the VF from the VM and Reconnecting to the PF of the Quick Start Guide.
Related Information
Level Two Title