SDI II Intel® Cyclone 10 GX FPGA IP Design Example User Guide
ID
683815
Date
12/12/2022
Public
2. SDI II Intel FPGA IP Design Example Detailed Description
The SDI II Intel FPGA IP core includes these design examples for Intel® Cyclone® 10 GX devices.
- Parallel loopback with external VCXO
- Parallel loopback without external VCXO
- Serial loopback
Features
- All designs use LED status for early debugging stage.
- The simplex serial loopback designs include RX and TX options. To use RX or TX only components, remove the irrelevant blocks from the designs.
User Requirement Preserve Remove RX Only RX Top - TX Top
TX Only TX Top - RX Top
Figure 9. Components Required for Intel® Cyclone® 10 GX TX or RX Only Design