2.4. Clocking Scheme Signals

SDI II Intel® Cyclone 10 GX FPGA IP Design Example User Guide

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Date 12/12/2022

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2.4. Clocking Scheme Signals

The table lists the clocking scheme signals for the SDI II Intel FPGA IP core design examples.

Table 14. Clocking Scheme Signals
Clock	Signal Name in Design	Description
TX PLL Refclock	`tx_pll_refclk`	TX PLL reference clock, of any frequency that is divisible by the transceiver for that data rate. You must connect this clock to a dedicated transceiver reference clock pin. Note: For 12G-SDI designs, Intel recommends to place the `refclk` pin within the same transceiver bank as the TX PLL block to ensure optimal jitter performance in your design. Parallel loopback with external VCXO Use a minimum clock frequency of 148.5 MHz (single-rate/triple-rate) or 297 MHz (multi-rate) to meet jitter performance specification. If you use a higher clock frequency, you would need to modify the TX PLL reference clock value in the TX PLL parameter editor. Parallel loopback without external VCXO The recommended frequency is 100 MHz. Serial loopback For this design, the TX PLL refclock is configured to generate clock for integer frame rate. Use a minimum clock frequency of 148.5 MHz (single-rate/triple-rate) or 297 MHz (multi-rate) to meet jitter performance specification. If you use a higher clock frequency, you would need to modify the TX PLL reference clock value in the TX PLL parameter editor.
TX PLL Alt Refclock	`tx_pll_refclk_alt`	Second TX PLL reference clock which can be any clock frequency that is divisible by transceiver for that data rate. This clock must be connected to a dedicated transceiver reference clock pin. Note: For 12G-SDI designs, Intel recommends to place the `refclk` pin within the same transceiver bank as the TX PLL block to ensure optimal jitter performance in your design. Serial loopback For this design example, TX PLL alt refclock is configured to generate clock for fractional frame rate. Use a minimum clock frequency of 148.35 MHz (single-rate/triple-rate) or 296.7 MHz (multi-rate) to meet jitter performance specification. If you use a higher clock frequency, you would need to modify the TX PLL reference clock value in the TX PLL parameter editor.
TX Transceiver Clockout	`tx_vid_clkout`	Recovered clock from the transceiver. HD-SDI single rate 74.25 MHz (default) 74.1758 MHz (for the Dynamic TX clock switching feature when you transmit video format with fractional frame rate) 3G-SDI single rate, triple rate or multi rate 148.5 MHz (default) 148.35 MHz (for the Dynamic TX clock switching feature when you transmit video format with fractional frame rate)
TX PLL Serial Clock	`tx_serial_clk`	Serial fast clock generated by TX PLL. The clock frequency is set based on the data rate.
RX Refclock	`rx_cdr_refclk`	Transceiver clock data recovery (CDR) reference clock, of any frequency divisible by the transceiver for that data rate. Only a single reference clock frequency is required to support both integer and fractional frame rates. It must be a free running clock connected to the transceiver clock pin. For Intel® Cyclone® 10 GX devices, the multi-rate designs use a clock frequency of 297 MHz and the single-rate and triple-rate designs use a frequency of 148.5 MHz. Using a higher clock frequency would require a modification of the RX CDR reference clock value in the Transceiver Native PHY Intel® Arria® 10/Cyclone 10 FPGA IP core parameter editor. For triple or multi-rate modes, you need to modify the reference clock value for every profile. Refer to the Changing RX CDR in Transceiver Native PHY IP Core section in the SDI II Intel FPGA IP User Guide. Note: Do not share the TX PLL reference clock with the RX transceiver reference clock for a parallel loopback design. In parallel loopback designs, the TX PLL clock is tuned to match the RX recovered clock frequency.
RX Refclock	`rx_core_refclk`	SDI RX core reference clock. The required frequency is 148.5/148.35 MHz or 297/296.7 MHz depending on what you specify for the Rx core clock (rx_coreclk) frequency parameter. This clock must be a free-running clock.
RX Transceiver Clkout	`rx_vid_clkout`	Recovered clock from the transceiver. SD-SDI 148.5 MHz (default) HD-SDI 74.25 MHz when receiving integer frame rate 74.1758 MHz when receiving fractional frame rate 3G/6G/12-SDI 148.5 MHz when receiving integer frame rate 148.35 MHz when receiving fractional frame rate
Management Clock	`rx_rcfg_mgmt_clk`	A free-running 100 MHz RX clock used by Avalon-MM interfaces for reconfiguration and by the PHY reset controller for transceiver reset sequence. 100 MHz frequency is used if you set the Rx core clock (rx_coreclk) frequency parameter to 297 MHz. Otherwise, the design example uses 148.5 MHz to share between this clock and `rx_coreclk`.
		Component	Required Frequency (MHz)
		Avalon-MM reconfiguration	100 – 125
		Transceiver PHY reset controller	1 – 500
		You may change the clock frequency as long as it is within the valid frequency range of the Avalon-MM reconfiguration and Transceiver PHY reset controller. For Transceiver PHY reset controller, you may need to modify the input clock frequency in the parameter editor.
	`tx_rcfg_mgmt_clk`	A free-running 100 MHz TX clock used by Avalon-MM interfaces for reconfiguration and by the PHY reset controller for transceiver reset sequence. 100 MHz frequency is used if you set the Rx core clock (rx_coreclk) frequency parameter to 297 MHz. Otherwise, the design example uses 148.5 MHz to share between this clock and `rx_coreclk`. Otherwise, 148.5 MHz is used to share between this clock and `rx_coreclk`.
		Component	Required Frequency (MHz)
		Avalon-MM reconfiguration	100 – 125
		Transceiver PHY reset controller	1 – 500
		You may change the clock frequency as long as it is within the valid frequency range of the Avalon-MM reconfiguration and Transceiver PHY reset controller. For Transceiver PHY reset controller, you may need to modify the input clock frequency in the parameter editor.