AN 294: Crosspoint Switch Matrices in Altera MAX Series

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ID 683806
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Crosspoint Switch Matrices in Altera MAX Series
1. Crosspoint Switch Matrices in Altera MAX Series x
1.1. Crosspoint Switches Using Supported Altera Devices 1.2. Implementation 1.3. Document Revision History
1.1. Crosspoint Switches Using Supported Altera Devices x
1.1.1. 16 × 16 Crosspoint Switch 1.1.2. Customized Crosspoint Switch
1.1.1. 16 × 16 Crosspoint Switch x
1.1.1.1. 16 × 16 Crosspoint Switch Architecture 1.1.1.2. Signals 1.1.1.3. Switch Matrix 1.1.1.4. Address Decoder 1.1.1.5. Configuration 1.1.1.6. Crosspoint Switch Expansion
1.1.1.6. Crosspoint Switch Expansion x
1.1.1.6.1. Source Code Modification 1.1.1.6.2. Multiple Device Implementation
1.1.2. Customized Crosspoint Switch x
1.1.2.1. Customized Crosspoint Switch Architecture 1.1.2.2. Configuration
1.2. Implementation x
1.2.1. Design Example: 16 × 16 Crosspoint Switch 1.2.2. Design Example: Customized Crosspoint Switch
1.2.1. Design Example: 16 × 16 Crosspoint Switch x
1.2.1.1. Reference Design Files Hierarchy 1.2.1.2. Reference Design Files 1.2.1.3. Design Utilization 1.2.1.4. Crosspoint Switch Expansion 1.2.1.5. Design Verification
1.2.2. Design Example: Customized Crosspoint Switch x
1.2.2.1. Cutomized Crosspoint Switch Configuration 1.2.2.2. Design Utilization 1.2.2.3. Design Verification
1. Crosspoint Switch Matrices in Altera MAX Series

1.2.2.3. Design Verification

You can verify the design for a 4-port customized crosspoint switch using the Quartus® II software. The design verification occurs in both functional and timing simulations.

Figure 8. 4-Port Customized Crosspoint Switch Timing Simulations

With all the I/O pins in tri-state mode, each port was initialized. After initialization, output configuration occurs for port_B and port_C, while input configuration occurs for port_A and port_D. Input port_A is connected to port_C and input port_D is connected to port_B. In the last configuration, output port_A and port_C are connected to input port_D, while port_B is tri-stated.

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