AN 294: Crosspoint Switch Matrices in Altera MAX Series

ID 683806
Date 9/22/2014
Public

1.1.1.4. Address Decoder

You can use an address decoder to decode the output address so that only one output cell is enabled for configuration.

Table 2.  Input and Output of a 4-Bit Decoder
Decoder Input [3..0] Decoder Output [15..0] Enabled Output Cells
0000 0000000000000001 Output 0
0001 0000000000000010 Output 1
0010 0000000000000100 Output 2
0011 0000000000001000 Output 3
0100 0000000000010000 Output 4
0101 0000000000100000 Output 5
0110 0000000001000000 Output 6
0111 0000000010000000 Output 7
1000 0000000100000000 Output 8
1001 0000001000000000 Output 9
1010 0000010000000000 Output 10
1011 0000100000000000 Output 11
1100 0001000000000000 Output 12
1101 0010000000000000 Output 13
1110 0100000000000000 Output 14
1111 1000000000000000 Output 15

The Quartus® II software synthesizes the decoder. You can use the product-term logic in MAX® 3000A device or in the look-up table (LUT) in MAX® II, MAX® V, and MAX® 10 devices to combine the decoding with other functions.

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