F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 10/02/2023
Document Table of Contents

4.4. QSF Assignments

For successful logic generation/compilation and simulation, you must specify colocate assignment to map F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP to F-Tile Ethernet Intel FPGA Hard IP in the .qsf file in your design.

Use the following command to specify colocate assignment:
set_instance_assignment -name IP_COLOCATE \
-from <ANLT IP hierarchical path>  -to <Ethernet hierarchical path> <tile type>