1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
1.1.2. Generating Two Separate Instances of IP Design
Figure 4. Procedure
- In the Intel® Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Intel® Quartus® Prime project, or File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device.
- Specify the device family Agilex 7 (F-Series/I-Series) and select device with F-tile for your design.
- Select Tools > IP Catalog to open the IP Catalog and select F-Tile Ethernet Intel FPGA Hard IP.
- Specify a top-level name <your_ip> and the folder for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
- Click Create. The IP parameter editor appears.
Figure 5. Example Design Tab
- On the IP tab, specify the parameters for your IP core variation. For exact IP parameter setting, refer to the Selected IP Parameter Settings table in the desired Design Example chapter.
- Specify the parameters in the Example Design tab.
- Under Available Example Designs, select Two separate instances of ANLT, ETH IP.
- Under Example Design Files, select the Simulation option to generate the testbench and the compilation-only project. Select the Synthesis option to generate the hardware design example.
- Under Generated HDL Format, select Verilog .
- Under Target Development Kit, select Agilex 7 I-Series Transceiver-SoC Development Kit or None. If you select a Specific Development Kit as the Target Development Kit, the design example is generated based on a specific device and it overwrites the device you selected in your project file. If you select None as the Target Development Kit, ensure the selected device is your targeted device and adjust the pin assignments in the .qsf file.
- Click the Generate Example Design button.
- The software generates an example design with two instances of AN/LT IP and Ethernet IP, as well as two instances of System PLL Clocks IP. You require these files to run simulation, compilation, and hardware testing.
- For the second instance of AN/LT IP starts with 32'h1020 0000 for easier addressing.