F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

3.2. Functional Description

When generating a design example with PTP option enabled, the software instantiates PTP-specific components.
Figure 14.  F-Tile Ethernet Intel FPGA Hard IP: Design Example with Enabled PTP
The F-Tile Ethernet Intel FPGA Hard IP design example includes the following components:
  • F-Tile Ethernet Intel FPGA Hard IP : Generated IP core with enabled PTP option.
  • F-Tile Reference and System PLL Clocks Intel® FPGA IP : Instantiate reference clock and system PLL. For information about supported system PLL modes, refer to F-Tile Ethernet Intel FPGA Hard IP . For information about this IP, refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.
  • Time-of-Day (TOD): Provides a continuous flow of a current time-of-day information to the IP core. The master TOD runs at 125 MHz clock frequency. TX TOD and RX TOD, which are clocked by div66 or div68 clock of the F-Tile Ethernet Intel FPGA Hard IP, synchronize to the master TOD through their respective TOD synchronizers.

    Master TOD also generates a one pulse per second (1 pps) to monitor the accuracy and allows synchronization between multiple devices.

    In this user guide, the generated design example assumes 0 ppm delay. In your design, drive the master TOD with the most accurate clock.

  • Packet Client: Consists of multiple PTP related modules. The Packet Client does not support the PTP functionality when packet loop back is set from RX to TX in client side.
  • Packet Generator: Configures to loop over various patterns in the ROM. Alternatively, can perform a single transmission.
  • PTP Command Generator: The PTP command generation module in the Packet Client generates PTP command for the packet in transmission. The generated command aligns to start-of-packet (SOP) for Avalon® streaming interface and MAC segmented based interface.
  • Packet Monitor: Stores sent and received packet information between packet client and the IP core.
  • PTP Monitor: The module stores the PTP information sent from/to the Packet Client to/from the F-Tile Ethernet Intel FPGA Hard IP when packet loop backs from TX serial to RX serial.
    Note: PTP Monitor can store and read 16 packets of 128 bytes in length. Sending more packets without first reading the contents of the PTP monitor can cause unexpected results.
  • PTP Adapter Module ( Avalon® memory-mapped interface for Asymmetry and Peer-to-Peer (P2P): If you enabled PTP option in the F-Tile Ethernet Intel FPGA Hard IP, you must instantiate this module and connect it to all associated Ethernet IP cores. The design allows only one instance per tile.

    When instantiated, the module provides the access to the Avalon® memory-mapped interface registers, specifically Asymmetry Delay and P2P MeanPathDelay registers.

  • Avalon® memory-mapped interface Decoder: Decodes the Avalon® memory-mapped interface address to Hardware IP Top, master TOD, and PTP adapter. For base address for each of the Avalon® memory-mapped interface accessed instances, refer to Register Maps.
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