F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 10/02/2023
Public
Document Table of Contents

8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.10.02 23.3 11.0.0 Updated a note about the design example simulation script enables the macro by default for all variants except for the variants with PTP enabled in Fast Sim Model for FHT Variants.
2023.04.03 23.1 9.0.0
  • Added new section: Two separate instances of Auto-Negotiation and Link Training and Ethernet IP Design
  • Added the following topics in the Two separate instances of Auto-Negotiation and Link Training and Ethernet IP Design.
    • Features
    • Functional Description
    • Simulation
    • QSF Assignments
    • Hardware Design Example
  • Added a note to the Testing the Hardware Design Example of the Quick Start Guide section.
  • Updated the product family name to "Intel Agilex 7."
2022.12.19 22.4 8.0.0 Made the following changes:
  • Added Aldec Riviera-PRO simulator and instruction in Simulating the Design example Testbench.
  • Removed Generating Tile Files section.
  • Removed a note about tile-related files generation, design_example_dir>/ex_*G/sim, and command to run the IP setup simulation in Simulating the Design Example Testbench.
  • Added new topic: Fast Sim Model for FHT Variants
  • Removed steps 5.a to 5.c to set frequencies for the design example in Compiling and Configuring the Design Example in Hardware.
  • Updated step 4 bullets in Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example.
    • internal_loop_back_bk Instance_number no_of_lanes
    • internal_loop_back_bk Instance _number no_of_lanes
  • Added a note about tx_board_dly and rx_board_dly in step 6.c Hardware Design Example of Design Example: Single IP Core Instantiation with Precision Time Protocol.
  • Added a note in step 11.b in Hardware Design Example of Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training.
  • Updated steps to generate tile-related files for successful simulation in the Simulation topic.
2022.09.26 22.3 7.0.0 Made the following changes:
  • Added screenshots for successful AN/LT hardware run in AN/LT Hardware Design Example.
  • Updated table 5: IP Parameters for 100G Ethernet Mode with 2 Lanes Design Example in Design Example: Single IP Core Instantiation.
  • Added note about PTP monitor in functional description of Design Example: Single IP Core Instantiation with Precision Time Protocol.
  • Added note about auto-negotiation and link training bonding support for B0 FHT multi-lane designs in functional description of Design Example: Single IP Core Instantiation with Auto- Negotiation and Link Training.
2022.06.20 22.2 6.0.0 Made the following changes:
  • Added clock controller screenshot and updated steps in Compiling and Configuring the Design Example in Hardware.
  • Updated Design Example: Single IP Core Instantiation with Precision Time Protocol:

    Updated steps in Hardware Design Example.

  • Removed note about i_reconfig_clk clock frequency limitation in Functional Description.
  • Added FGT and FHT macros to simulation run script for AN/LT enabled designs in simulation.
2022.01.30 21.4 4.0.0
  • Added support for the Xcelium* simulator.
  • Updated quick start guide sub-sections:
    • Globally added support for the Agilex I-Series Transceiver-SoC Development Kit.
    • Updated Generating Tile Files.
    • Added new topic: Compiling and Configuring the Design Example in Hardware.
    • Updated steps in Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example.
  • Updated Design Example: Single IP Core Instantiation with Precision Time Protocol:
    • Added note about i_reconfig_clk clock frequency limitation.
    • Revised the sample output in the Simulation section.
    • Added new topic: Hardware Design Example.
  • Updated Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training:
    • Replaced the placement assignments with the colocate assignments.
    • Updated simulation flow.
    • Updated QSF assignments.
2021.10.11 21.3 3.0.0
  • Added pin assignment requirement for AN/LT designs in Generating Tile Files.
  • Updated the list of supported simulators in Simulating the Design Example Testbench.
  • Added new topics:
    • Fast Sim Model
    • Testing the Hardware Design Example
    • Register Maps
    • Simulation Testbench Flow for PCS, OTN, and FlexE Modes
  • Updated register descriptions in Packet Client Registers.
  • Updated PTP-related Registers section. Address offset is specified as a byte address.
  • Added new design examples: Single IP Core Instantiation with Auto-Negotiation and Link Training
2021.07.01 21.2 2.0.0 Initial release.