1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
1.3.1. Fast Sim Model for FGT Variants
To provide a reduction in a real-time simulation duration, you can utilize a Fast Sim model in your design example testbench. For FGT variants, the model is enabled by a macro in the simulation run script.
To enable the Fast Sim model, add the following macro to your simulation run script:
+define+IP7581SERDES_UX_SIMSPEEDThe design example simulation script enables the macro by default for all variants with the exception of variants with enabled PTP or auto-negotiation and link training.
- In PTP variants, the macro is not enabled by default as it affects the timestamp accuracy in simulation. If you want to perform a general functionality check, you can enable the macro in your PTP simulation scripts.
- The macro is not available for designs with enabled auto-negotiation and link training
- You can achieve faster simulation times with auto-negotiation and link training enabled designs by running i_reconfig_clk at 10GHz. Furthermore, you can skip auto-negotiation and link training functionality and go directly to Data/Ethernet mode by writing to auto-negotiation and link training Control Status Registers (CSRs) or GUI parameters.
You can also add the macro to your simulation script for your own testbench.
Attention: In 53G PAM4 Ethernet IPs, you must set the serial clock input to the IP to the exact value of 37.648 ps for simulation to work correctly. This limitation does not apply to the design example simulations since the serial lines are in a loopback.