F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 1/30/2022
Public

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5.3. Simulation

The testbench provides basic functionality such as the startup and wait for lock, sending and receiving of a few packets per each instantiated IP using the ROM-based packet generator.
Figure 15. Simulation Design Example Block Diagram with 2 instantiated F-Tile Ethernet Intel FPGA Hard IPs
The following steps show the simulation testbench flow:
  1. Assert global reset (i_rst_n) to reset each F-Tile Ethernet Intel FPGA Hard IP instance (IP instance).
  2. Wait until resets acknowledgment from all IP instances. The o_rst_ack_n signals go low.
  3. Deasserts the global reset.
  4. Wait until o_tx_lanes_stable bit is set to 1, indicating TX path is ready.
  5. Wait until o_rx_pcs_ready bit is set to 1, indicating RX path is ready.
  6. Repeat steps 4 and 5 to complete the reset sequence for all IP instances.
  7. Instruct packet client to transmit data. Write hw_pc_ctrl[0]=1'b1 to start the packet generator.
  8. Read TX packet data information from 0x20 - 0x34 registers. Read registers in a sequential order.
  9. Read RX packet data information from 0x38 - 0x4C registers. Read registers in a sequential order.
  10. Compare the counters to ensure 16 packets were sent and received.
  11. Instruct packet client to stop data transmission. Write hw_pc_ctrl[2:0]=3'b100 to stop the packet generator. Clear counters.
  12. Repeat steps 7 - 11 to simulate packet transfer for each of the instantiated IPs.
  13. Perform Avalon® memory-mapped interface test. Write and read Ethernet IP registers.
  14. Perform Avalon® memory-mapped interface 2 test to read and write operation transceiver registers.
  15. Repeat steps 13 and 14 for each instantiated IP in a sequential order.
The following sample output illustrates a successful simulation test run.

---SRC IP sequence started -----
---SRC IP sequence TX completed -----
---SRC IP sequence RX completed -----
---Test    0;   ---Total     16 packets to send-----
------Start pkt gen TX-----
------Checking Packet TX/RX result-----
------------  16 packets Sent;     0 packets Received--------
------ALL   16  packets Sent out---
------------  16 packets Sent;    16 packets Received--------
------ALL   16  packets Received---
------TX/RX packet check OK---
****Starting AVMM Read/Write****
====>MATCH!     ReaddataValid = 1 Readdata = abcdef01 Expected_Readdata = abcdef01 
====>MATCH!     ReaddataValid = 1 Readdata = 00000007 Expected_Readdata = 00000007 
====>MATCH!     ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 
====>MATCH!     ReaddataValid = 1 Readdata = 9d228c3a Expected_Readdata = 9d228c3a 
====>MATCH!     ReaddataValid = 1 Readdata = 4338b586 Expected_Readdata = 4338b586 
====>MATCH!     ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 
====>MATCH!     ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 
====>MATCH!     ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 
====>MATCH!     ReaddataValid = 1 Readdata = 22334455 Expected_Readdata = 22334455 
====>MATCH!     ReaddataValid = 1 Readdata = 00000011 Expected_Readdata = 00000011 
====>MATCH!     ReaddataValid = 1 Readdata = 000005ee Expected_Readdata = 000005ee 
====>MATCH!     ReaddataValid = 1 Readdata = 01234567 Expected_Readdata = 01234567 
====>MATCH!     ReaddataValid = 1 Readdata = 000089ab Expected_Readdata = 000089ab 
743830ns  Try to access AVMM2 begin...
743830ns  write 0x00000065 to xcvr  0 address 0x103c004
744795ns  Try to access AVMM2 end...
744890ns  read from address 0x103c004
====>MATCH!     ReaddataValid = 1 Readdata = 00000065 Expected_Readdata = 00000065 

...

758740ns  Try to access AVMM2 end...
758840ns  Try to access AVMM2 begin...
758840ns  write 0x0000006c to xcvr  7 address 0x103c00b
759825ns  Try to access AVMM2 end...
759920ns  read from address 0x103c00b
====>MATCH!     ReaddataValid = 1 Readdata = 0000006c Expected_Readdata = 0000006c 
760900ns  Try to access AVMM2 end...
**** AVMM Read/Write Operation Completed ****
** Testbench complete
**

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