F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 1/30/2022
Public

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Document Table of Contents

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 4.0.0
The F-Tile Ethernet Intel® FPGA Hard IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates an example design with all files necessary to compile and test the design in hardware. The simulation example design contains a simple testbench used to exercise the hardware example design.

You can generate a design example for any supported variants including design examples with Media Access Controller (MAC) interface, Physical Coding Sublayer (PCS) interface, Optical Transport Network (OTN) interface, and Flexible Ethernet (FlexE) interface for various Ethernet modes and optional FEC mode. In your design example, you can also enable the Precision Time Protocol (PTP) and auto-negotiation and link training options. For a list of supported configurations in the current Intel® Quartus® Prime Pro Edition software version, refer to the Variant Selection table in the F-Tile Ethernet Intel FPGA Hard IP User Guide.

This user guide describes the following design examples:
Note: The current Intel® Quartus® Prime Pro Edition software release does not support 40GE/50GE/100GE OTN design examples with no FEC.
Figure 1. Development Stages for the Design ExampleFuture IP core releases also provide a hardware design example you can compile and test in hardware.

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