F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 1/30/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Generating Tile Files 1.4. Simulating the Design Example Testbench 1.5. Hardware and Software Requirements 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.8. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.4. Simulating the Design Example Testbench x
1.4.1. Fast Sim Model for FGT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 4.0.0
The F-Tile Ethernet Intel® FPGA Hard IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates an example design with all files necessary to compile and test the design in hardware. The simulation example design contains a simple testbench used to exercise the hardware example design.

You can generate a design example for any supported variants including design examples with Media Access Controller (MAC) interface, Physical Coding Sublayer (PCS) interface, Optical Transport Network (OTN) interface, and Flexible Ethernet (FlexE) interface for various Ethernet modes and optional FEC mode. In your design example, you can also enable the Precision Time Protocol (PTP) and auto-negotiation and link training options. For a list of supported configurations in the current Intel® Quartus® Prime Pro Edition software version, refer to the Variant Selection table in the F-Tile Ethernet Intel FPGA Hard IP User Guide.

This user guide describes the following design examples:
Note: The current Intel® Quartus® Prime Pro Edition software release does not support 40GE/50GE/100GE OTN design examples with no FEC.
Figure 1. Development Stages for the Design ExampleFuture IP core releases also provide a hardware design example you can compile and test in hardware.
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