F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 1/30/2022
Public

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Document Table of Contents

7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.01.30 21.4 4.0.0
  • Added support for the Xcelium* simulator.
  • Updated quick start guide sub-sections:
    • Globally added support for the Agilex I-Series Transceiver-SoC Development Kit.
    • Updated Generating Tile Files.
    • Added new topic: Compiling and Configuring the Design Example in Hardware.
    • Updated steps in Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example.
  • Updated Design Example: Single IP Core Instantiation with Precision Time Protocol:
    • Added note about i_reconfig_clk clock frequency limitation.
    • Revised the sample output in the Simulation section.
    • Added new topic: Hardware Design Example.
  • Updated Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training:
    • Replaced the placement assignments with the colocate assignments.
    • Updated simulation flow.
    • Updated QSF assignments.
2021.10.11 21.3 3.0.0
  • Added pin assignment requirement for AN/LT designs in Generating Tile Files.
  • Updated the list of supported simulators in Simulating the Design Example Testbench.
  • Added new topics:
    • Fast Sim Model
    • Testing the Hardware Design Example
    • Register Maps
    • Simulation Testbench Flow for PCS, OTN, and FlexE Modes
  • Updated register descriptions in Packet Client Registers.
  • Updated PTP-related Registers section. Address offset is specified as a byte address.
  • Added new design examples: Single IP Core Instantiation with Auto-Negotiation and Link Training
2021.07.01 21.2 2.0.0 Initial release.

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