AN 630: Real-Time ISP and ISP Clamp for Intel® MAX® Series Devices

ID 683786
Date 5/27/2022

How Real-Time ISP Works

In a normal ISP operation, the new design data is downloaded from the configuration flash memory (CFM) to the SRAM after the completion of CFM programming. During the programming and downloading processes, the I/O pins remain tri-stated. After the download is completed, the device resets and enters user mode operation.

Figure 1. Normal ISP Operation

In real-time ISP mode, the user flash memory (UFM), programmable logic, and I/O pins remain operational during the progress of the CFM programming. After programming is successful, the device waits for a power cycle to occur, and then the CFM contents are downloaded to SRAM as part of a normal power-up sequence. After tCONFIG time, the device enters user mode.

Figure 2. Real-Time ISP Operation