AN 630: Real-Time ISP and ISP Clamp for Intel® MAX® Series Devices

ID 683786
Date 5/27/2022

How ISP Clamp Works

You can set the I/O pins to tri-state (default), high, or low states; or sample and sustain the existing pin state in the ISP clamp operation. The Intel® Quartus® Prime software assigns the state values to scan into the boundary-scan registers of each I/O pin based on your settings. These values determine the state of the pins to be clamped while programming the device. When the ISP clamp feature is used, the weak I/O pull-up resistors are disabled during programming even if the I/O is clamped to a tri-state value.

Before clamping the I/O pins, the SAMPLE/PRELOAD JTAG instruction is first executed to load the values to the boundary-scan registers. The EXTEST instruction is then executed to clamp the I/O pins to the values loaded into the boundary-scan registers during SAMPLE/PRELOAD.

If you choose to sample and hold the existing state of a pin when the device enters ISP clamp mode, ensure that the signal is in a steady state. You need a steady state signal because you cannot control the sample set-up time as it depends on the TCK frequency as well as the download cable and software. You might not capture the correct value if you sample a signal that toggles or is not static for long periods of time.

Figure 6. ISP Clamp Operation