Arria 10 FPLL IP Core Release Notes

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ID 683784
Date 10/31/2016
Public
Document Table of Contents
Document Table of Contents x
1. Arria 10 FPLL IP Core Release Notes
1. Arria 10 FPLL IP Core Release Notes x
1.1. Arria 10 FPLL IP Core Revision History v16.1 Revision History 1.2. Arria 10 FPLL IP Core Revision History v15.1 Revision History 1.3. Arria 10 FPLL IP Core Revision History v15.0 Revision History 1.4. Arria 10 FPLL IP Core Revision History v14.1 Revision History 1.5. Arria 10 FPLL IP Core Revision History v14.0 Revision History 1.6. Arria 10 FPLL IP Core Revision History v13.1 Revision History
1. Arria 10 FPLL IP Core Release Notes

1.1. Arria 10 FPLL IP Core Revision History v16.1 Revision History

Table 1.  v16.1 October 2016
Description Impact

Issue: During Arria 10 FPLL reconfiguration, pll_locked signal can deassert indicating that FPLL loses lock to reference clock. The behavior is limited to the condition when reference clock pll_refclk<n> changes at the same time with FPLL reconfiguration.

Workaround: No.

Resolution: The simulation model in Quartus Prime 16.1 is updated to fix the behaviour.

Simulation only. Silicon is not affected.
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