Arria 10 FPLL IP Core Release Notes

ID 683784
Date 10/31/2016

1.5. Arria 10 FPLL IP Core Revision History v14.0 Revision History

Table 5.  v14.0 Arria 10 Edition August 2014
Description Impact
Upgraded to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores. -
Added support for Embedded debug feature. This feature enables you to write to the PLL control registers and read from status registers for the PLL instances in the design. This feature is available under the Dynamic Reconfiguration tab. -
Changed the FPLL Parameter Editor graphic user interface (GUI) to show the available FPLL modes. You can use the FPLL in the following three modes:
  • Core
  • Cascade Source
  • Transceiver
Removed the option for automatic bandwidth setting. The following bandwidth settings are available:
  • Low
  • Medium
  • High
Enhanced user warnings and information messages. -
The fPLL IP in 13.1 Arria 10 edition, allowed simultaneous selection of FPLL to be used in core and transceiver PLL modes. However, in the FPLL IP in 14.0 Arria 10 edition, only one mode (transceiver PLL or core PLL) can be selected at a time. If you have selected both (transceiver PLL and core PLL) modes in 13.1 Arria 10 edition, then FPLL IP will fail automatic upgrade for 14.0 Arria 10 edition. In this case, you will have to manually upgrade the FPLL IP after selecting one legal FPLL usage mode. -
The Master Clock Generation Block tab in IP Parameter Editor is not visible when "Core" is selected as the FPLL mode. The Master Clock Generation Block tab appears only when "Transceiver" is selected as the FPLL mode. -

Did you find the information on this page useful?

Characters remaining:

Feedback Message