Arria 10 FPLL IP Core Release Notes

ID 683784
Date 10/31/2016

1.2. Arria 10 FPLL IP Core Revision History v15.1 Revision History

Table 2.  v15.1 Novembver 2015
Description Impact
Changed the "Enable cascade clock input port" parameter name to "Enable ATX to FPLL cascade clock input port."

Issue: ACDS 15.1 introduces a necessary fix for Arria 10 transceiver designs. This fix introduces a change that affects post-fit simulation for designs containing Arria 10 Transceiver Native PHY, Arria 10 Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, and Arria 10 fPLL IP cores.

pll_powerdown is not connected for HSSI PLL IPs.

Workaround: Users requiring post-fit simulation of the transceiver PLLs in ACDS 15.1 need to disable the "Transceiver Reset Sequencer" for their design to produce a post-fit simulation netlist. However, this cannot and should not be used to produce the final bitstream for hardware. Hardware requires the "Transceiver Reset Sequencer" to be enabled.

To disable the "Transceiver Reset Sequencer" in the Quartus Prime software, add the following QSF to the Quartus Settings File for the project:

set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS=1"

This will completely disable the reset sequencer in the design and restore the old behavior. This method does not allow post-fit simulation of the "Transceiver Reset Sequencer" logic.

Resolution: A modification to the PLL simulation models is planned for a subsequent release of ACDS 15.1 to remove the reset requirement.

pll_powerdown inputs to the Arria 10 Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, and Arria 10 fPLL IP cores for Quartus Prime synthesis. As a result, the resulting generated post-fit simulation will not have a reset input connection for the PLL and post-fit simulation will likely fail.

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