Quartus® Prime Pro Edition User Guide: PCB Design Tools

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Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Signal Integrity Analysis with Third-Party Tools 2. Reviewing Printed Circuit Board Schematics with the Quartus® Prime Software 3. Siemens EDA PCB Design Tools Support 4. Cadence Board Design Tools Support 5. Quartus® Prime Pro Edition User Guide: PCB Design Tools Document Archives A. Quartus® Prime Pro Edition User Guides
1. Signal Integrity Analysis with Third-Party Tools x
1.1. Signal Integrity Analysis with Third-Party Tools 1.2. I/O Model Selection: IBIS or HSPICE 1.3. FPGA to Board Signal Integrity Analysis Flow 1.4. Simulation with IBIS Models 1.5. Simulation with HSPICE Models 1.6. Signal Integrity Analysis with Third-Party Tools Document Revision History
1.1. Signal Integrity Analysis with Third-Party Tools x
1.1.1. What's New In This Version 1.1.2. Signal Integrity Simulations with HSPICE and IBIS Models
1.3. FPGA to Board Signal Integrity Analysis Flow x
1.3.1. Create I/O and Board Trace Model Assignments 1.3.2. Customize the Output Files 1.3.3. Set Up and Run Simulations in Third-Party Tools 1.3.4. Interpret Simulation Results
1.4. Simulation with IBIS Models x
1.4.1. IBIS Model Access and Customization Flows 1.4.2. Elements of an IBIS Model 1.4.3. Customizing IBIS Models 1.4.4. Design Simulation Using the Siemens EDA HyperLynx* Software 1.4.5. Configuring LineSim to Use Intel IBIS Models 1.4.6. Integrating Intel IBIS Models into LineSim Simulations 1.4.7. Running and Interpreting LineSim Simulations
1.4.3. Customizing IBIS Models x
1.4.3.1. Generate Custom IBIS Models with the EDA Netlist Writer GUI 1.4.3.2. Customizing Downloaded or Installed IBIS Model Files for Agilex™ FPGA Portfolio Devices 1.4.3.3. Customizing Downloaded IBIS Models for Stratix® 10 Devices, Arria® 10 Devices, and Cyclone® 10 GX Devices
1.4.3.1. Generate Custom IBIS Models with the EDA Netlist Writer GUI x
1.4.3.1.1. Board Level Signal Integrity Analysis Settings
1.5. Simulation with HSPICE Models x
1.5.1. Supported Devices and Signaling 1.5.2. Accessing HSPICE Simulation Kits 1.5.3. The Double Counting Problem in HSPICE Simulations 1.5.4. HSPICE Writer Tool Flow 1.5.5. Running an HSPICE Simulation 1.5.6. Interpreting the Results of an Output Simulation 1.5.7. Interpreting the Results of an Input Simulation 1.5.8. Viewing and Interpreting Tabular Simulation Results 1.5.9. Viewing Graphical Simulation Results 1.5.10. Making Design Adjustments Based on HSPICE Simulations 1.5.11. Sample Input for I/O HSPICE Simulation Deck 1.5.12. Sample Output for I/O HSPICE Simulation Deck 1.5.13. Advanced Topics
1.5.3. The Double Counting Problem in HSPICE Simulations x
1.5.3.1. Defining the Double Counting Problem 1.5.3.2. The Solution to Double Counting
1.5.4. HSPICE Writer Tool Flow x
1.5.4.1. Applying I/O Assignments 1.5.4.2. Enabling HSPICE Writer Using Assignments 1.5.4.3. Naming Conventions for HSPICE Files 1.5.4.4. Invoking HSPICE Writer 1.5.4.5. Invoking HSPICE Writer from the Command Line 1.5.4.6. Customizing Automatically Generated HSPICE Decks
1.5.11. Sample Input for I/O HSPICE Simulation Deck x
1.5.11.1. Header Comment 1.5.11.2. Simulation Conditions 1.5.11.3. Simulation Options 1.5.11.4. Constant Definition 1.5.11.5. Buffer Netlist 1.5.11.6. Drive Strength 1.5.11.7. I/O Buffer Instantiation 1.5.11.8. Board Trace and Termination 1.5.11.9. Stimulus Model 1.5.11.10. Simulation Analysis
1.5.12. Sample Output for I/O HSPICE Simulation Deck x
1.5.12.1. Header Comment 1.5.12.2. Simulation Conditions 1.5.12.3. Simulation Options 1.5.12.4. Constant Definition 1.5.12.5. I/O Buffer Netlist 1.5.12.6. Drive Strength 1.5.12.7. Slew Rate and Delay Chain 1.5.12.8. I/O Buffer Instantiation 1.5.12.9. Board and Trace Termination 1.5.12.10. Double-Counting Compensation Circuitry 1.5.12.11. Simulation Analysis
1.5.13. Advanced Topics x
1.5.13.1. PVT Simulations 1.5.13.2. Hold Time Analysis 1.5.13.3. I/O Voltage Variations 1.5.13.4. Correlation Report
2. Reviewing Printed Circuit Board Schematics with the Quartus® Prime Software x
2.1. Reviewing Quartus® Prime Software Settings 2.2. Reviewing Device Pin-Out Information in the Fitter Report 2.3. Reviewing Compilation Error and Warning Messages 2.4. Using Additional Quartus® Prime Software Features 2.5. Using Additional Quartus® Prime Software Tools 2.6. Reviewing Printed Circuit Board Schematics with the Quartus® Prime Software Revision History
2.1. Reviewing Quartus® Prime Software Settings x
2.1.1. Device and Pins Options Dialog Box Settings
2.1.1. Device and Pins Options Dialog Box Settings x
2.1.1.1. Configuration Settings 2.1.1.2. Unused Pin Settings 2.1.1.3. Dual-Purpose Pins Settings 2.1.1.4. Voltage Settings 2.1.1.5. Error Detection CRC Settings
2.5. Using Additional Quartus® Prime Software Tools x
2.5.1. Pin Planner
3. Siemens EDA PCB Design Tools Support x
3.1. Integrating with DxDesigner 3.2. Siemens EDA PCB Design Tools Support Revision History
3.1. Integrating with DxDesigner x
3.1.1. DxDesigner Project Settings 3.1.2. Creating Schematic Symbols in DxDesigner
4. Cadence Board Design Tools Support x
4.1. Cadence PCB Design Tools Support 4.2. Product Comparison 4.3. FPGA-to-PCB Design Flow 4.4. Setting Up the Quartus® Prime Software 4.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software 4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software 4.7. Cadence Board Design Tools Support Revision History
4.3. FPGA-to-PCB Design Flow x
4.3.1. Integrating Intel FPGA Designs
4.4. Setting Up the Quartus® Prime Software x
4.4.1. Generating a .pin File
4.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software x
4.5.1. Creating Symbols 4.5.2. Instantiating the Symbol in the Cadence Allegro Design Entry HDL Software
4.5.1. Creating Symbols x
4.5.1.1. Cadence Allegro PCB Librarian Part Developer Tool
4.5.1.1. Cadence Allegro PCB Librarian Part Developer Tool x
4.5.1.1.1. Cadence Allegro PCB Librarian Part Developer Tool in the Design Flow 4.5.1.1.2. Import and Export Wizard 4.5.1.1.3. Editing and Fracturing Symbol 4.5.1.1.4. Updating FPGA Symbols
4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software x
4.6.1. Creating a Cadence Allegro Design Entry CIS Project 4.6.2. Generating a Part 4.6.3. Generating Schematic Symbol 4.6.4. Splitting a Part 4.6.5. Instantiating a Symbol in a Design Entry CIS Schematic 4.6.6. Intel Libraries for the Cadence Allegro Design Entry CIS Software
4.6.6. Intel Libraries for the Cadence Allegro Design Entry CIS Software x
4.6.6.1. Using the Intel-provided Libraries with your Cadence Allegro Design Entry CIS Project
Answers to Top FAQs
1. Signal Integrity Analysis with Third-Party Tools
2. Reviewing Printed Circuit Board Schematics with the Quartus® Prime Software
3. Siemens EDA PCB Design Tools Support
4. Cadence Board Design Tools Support
5. Quartus® Prime Pro Edition User Guide: PCB Design Tools Document Archives
A. Quartus® Prime Pro Edition User Guides

1.6. Signal Integrity Analysis with Third-Party Tools Document Revision History

Table 4.  Document Revision History
Date Quartus® Prime Version Changes
2024.04.01 24.1
  • Updated throughout for initial Altera rebranding.
  • Updated What's New In This Version topic for latest software changes impacting this document.
  • Updated Signal Integrity Analysis with Third-Party Tools topic for removal of Enable Advanced I/O Timing option.
  • Updated Create I/O and Board Trace Model Assignments topic for removal of Enable Advanced I/O Timing option.
  • Updated Customize the Output Files topic for removal of Enable Advanced I/O Timing option.
  • Updated IBIS Model Access and Customization Flows topic for EDA Netlist Writer and Agilex™ FPGA portfolio device support.
  • Updated Generate Custom IBIS Models with the EDA Netlist Writer GUI topic to reflect Agilex™ FPGA portfolio device support.
  • Updated Customizing Downloaded or Installed IBIS Model Files for Agilex™ FPGA Portfolio Devices topic for EDA Netlist Writer IBIS model generation support.
  • Updated Simulation with HSPICE Models topic for removal of Enable Advanced I/O Timing option.
2023.08.01 23.1
  • Corrected junk characters in all code samples of Sample Input for I/O HSPICE Simulation Deck section.
  • Corrected junk characters in all code samples of Sample Output for I/O HSPICE Simulation Deck section.
2023.04.03 23.1
  • Added Top FAQs navigation to front cover.
  • Added What's New In This Version section.
  • Revised Third-Party Board Signal Integrity Analysis Flow diagram to reflect new IBIS file methods.
  • Revised Customize the Output Files topic to reflect new IBIS file methods.
  • Revised Simulation with IBIS Models topic to reflect new IBIS file methods.
  • Added IBIS Model Access and Customization topic.
  • Revised Customizing IBIS Models topic to reflect new IBIS file methods.
  • Added new Customizing Downloaded IBIS Models for Stratix® 10 Devices, Arria® 10 Devices, and Cyclone® 10 GX Devices topic.
  • Added new Generate Custom IBIS Models with the EDA Netlist Writer GUI for Stratix® 10 Devices, Arria® 10 Devices, and Cyclone® 10 GX Devices topic.
  • Added new Customizing IBIS Model Files for Agilex™ 7 Devices topic.
  • Update Design Simulation Using the Siemens EDA HyperLynx* Software topic for vendor name.
2017.11.06 17.1
  • Reorganized chapter introduction.
2016.10.31 16.1
  • Implemented Intel rebranding.
  • Corrected statement about timing simulation and double counting.
2015.11.02 15.1
  • Changed instances of Quartus II to Quartus® Prime .
June 2014 14.0 Updated format.
December 2010 10.0 Template update.
July 2010 10.0 Updated device support.
November 2009 9.1 No change to content.
March 2009 9.0
  • Was volume 3, chapter 12 in the 8.1.0 release.
  • No change to content.
November 2008 8.1
  • Changed to 8-1/2 x 11 page size.
  • Added information for Stratix III devices.
  • Input signals for Cyclone III devices are supported.
May 2008 8.0
  • Updated “Introduction” on page 12–1.
  • Updated Figure 12–1.
  • Updated Figure 12–3.
  • Updated Figure 12–13.
  • Updated “Output File Generation” on page 12–6.
  • Updated “Simulation with HSPICE Models” on page 12–17.
  • Updated “Invoking HSPICE Writer from the Command Line” on page 12–22.
  • Added “Sample Input for I/O HSPICE Simulation Deck” on page 12–29.
  • Added “Sample Output for I/O HSPICE Simulation Deck” on page 12–33.
  • Updated “Correlation Report” on page 12–41.
  • Added hyperlinks to referenced documents and websites throughout the chapter.
  • Made minor editorial updates.
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