Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

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ID 683763
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices 7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations
1.3.1. CvP Limitations x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe Wake-Up Time Requirement
4.1.2. PCIe Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel® Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing Open Source CvP Driver in Linux Systems 6.1.5.2. Setting Up the Correct MSEL Switch State 6.1.5.3. Programming CvP Images
6.1.5.1. Installing Open Source CvP Driver in Linux Systems x
6.1.5.1.1. Downstream open source CvP Driver 6.1.5.1.2. Upstream open source CvP Driver
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting Up the Base Revision 6.2.4. Setting Up and Compile the Updated Revision 6.2.5. Converting the SOF File 6.2.6. Programming the Core RBF file from the Updated Revision via PCIe Link
6.2.3. Setting Up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices
7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

2.4. Pin Description

The following table lists the CvP pin descriptions and connection guidelines:
Table 3.  CvP Pin Descriptions and Connection Guidelines
Pin Name Pin Type Pin Description Pin Connection SDM_IO Pins
CVP_CONFDONE Output The CVP_CONFDONE pin indicates the device has received the complete bitstream during configuration via protocol (CvP) core image configuration.

When used for this purpose, enable this pin using the Intel Quartus Prime software.

Connect this output pin to an external logic device that monitors the CvP operation. The VCCIO_SDM power supply must meet the input voltage specification of the receiving side.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16
INIT_DONE Output The INIT_DONE pin indicates the device has enter user mode upon completion of configuration. To use INIT_DONE to indicate user mode entry, you must enable it in the Intel® Quartus® Prime software.

When the INIT_DONE function is enabled, this pin drives high when configuration is completed and the device goes into user mode.

Intel® recommends you to use SDM_IO0 or SDM_IO16 to implement the INIT_DONE function when available as it has an internal weak pull-down for the correct function of INIT_DONE during power up.

If SDM_IO0 and SDM_IO16 are unavailable, the INIT_DONE function can also be implemented using any unused SDM_IO pins provided that an external 4.7–kΩ pull-down resistor is provided for the INIT_DONE signal.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16
CONF_DONE Output The CONF_DONE pin indicates all configuration data has been received.

By default, Intel recommends using the SDM_IO16 pin to implement the CONF_DONE function. If SDM_IO16 is unavailable, the CONF_DONE function can also be implemented using any unused SDM_IO pins. Except for SDM_IO0 and SDM_IO16, other SDM_IO pins are required to connect to an external 4.7-kΩ pull-down resistor for the CONF_DONE signal. Connect the CONF_DONE pin to the external configuration controller when configuring using the Avalon-ST (AVST) interface.

You have an option to monitor this signal with an external component if you are using the active serial (AS) x4 configuration scheme

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16
I_PIN_PERST_N_U[10,20]_P Input PCIe* Platform reset pin In a PCIe* adapter card implementation, connect the PCIe nPERST signal from the PCIe edge connector to each P-tile transceiver bank I_PIN_PERST_N input.

Use a level translator to fan out and change the 3.3V opendrain nPERST signal from the PCIe connector to the 1.8V I_PIN_PERST_N input of each P-tile transceiver that is used on the board.

Provide a 1.8V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe connector is an opendrain signal. You must pull up the 3.3V PCIe nPERST signal on the adapter card.

For non-PCIe systems, connect the system's master reset signal to the I_PIN_PERST_N input pin. If the master reset is not 1.8V, use a level shifter to meet the 1.8V I_PIN_PERST_N input requirement. For open-drain master reset driving the I_PIN_PRST_N input, provide a 1.8V pull-up resistor. Ensure all power to the device as well as the PCIe clock is stable prior to releasing the reset to the I_PIN_PRST_N pin.

This input pin does not have an internal pull-up resistor, you need to add an external 5kΩ – 10kΩ pull-up resistor if the voltage translator does not provide an active driver. If the tile is unused, tie to GND.

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