Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

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ID 683763
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices 7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations
1.3.1. CvP Limitations x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe Wake-Up Time Requirement
4.1.2. PCIe Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel® Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing Open Source CvP Driver in Linux Systems 6.1.5.2. Setting Up the Correct MSEL Switch State 6.1.5.3. Programming CvP Images
6.1.5.1. Installing Open Source CvP Driver in Linux Systems x
6.1.5.1.1. Downstream open source CvP Driver 6.1.5.1.2. Upstream open source CvP Driver
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting Up the Base Revision 6.2.4. Setting Up and Compile the Updated Revision 6.2.5. Converting the SOF File 6.2.6. Programming the Core RBF file from the Updated Revision via PCIe Link
6.2.3. Setting Up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices
7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

6.2.4. Setting Up and Compile the Updated Revision

Create a new revision to serve as the updated revision for the base design. The new revision uses a new core logic while re-uses the root partition exported from the base revision.

Follow these steps to create and compile an updated revision:

  1. On the Project menu, click Revisions. The Revisions window appears.
  2. To create a new revision, double-click <<new revision>>. The Create Revision window appears.
  3. In the Revision name: field, specify the revision name.
  4. In the Based on revision: field, select the base design.
  5. Enable This project uses a Partition Database (.qdb) file for the root partition box. In the Root Partition Database file:, select the root_partition.qdb generated from the base design.
    Note: This setting is also available in the Design Partitions window.
  6. In the Revision type: field, leave the option blank. The tool copies the type from the Based on revision: field.
  7. Click OK. The Intel® Quartus® Prime software exits the previous base design and loads the new design revision. The new design revision opens automatically. You can confirm the current revision by the Intel® Quartus® Prime software top tool bar menu.
  8. In the Design Partitions window, remove root_partition.qdb file from the Post Final Export File column.
  9. Create a new instance or module to replace or update the partition.
    For example, if you use <logic_name1> logic within the reserved core partition, and then change the <logic_name1> logic to <logic_name2> via entity rebinding, it replaced the <logic_name1> instance with the <logic_name2> instance.
  10. In the Design Partitions window, use the entity rebinding assignment to change the logic associated with the reserved core partition. Select the Entity Re-binding column when you use the entity rebinding assignment.
  11. In the Intel® Quartus® Prime software, click Assignments > Settings > Files and add <logic_name2>.v file. Remove the <logic_name1>.v file once you added <logic_name2>.v file.
  12. Verify the following lines in the .qsf file: 
    set_instance_assignment -name ENTITY_REBINDING <logic_name2> \
-to led_inst -entity top
  13. Click Processing > Start Compilation to run the design compilation.
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