1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices 7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel® Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices
1.3.1. CvP Limitations
The Intel® Agilex™ device CvP implementation has the following limitations and restrictions in the current version of the Intel® Quartus® Prime software:
- Only MemWR transactions can be used to write fabric configuration data to the CvP data register. ConfigWR transactions are not supported.
- When you poll the CVP_CREDIT bits from the CvP credit register, you must write the next 4KB of fabric configuration data to the CvP data register within 50 ms of receiving an additional credit. Failure to send the data results in configuration failure.
- The CvP response time is variable and depends on different conditions. The typical delay time is 5 sec and it is safe to wait till 1 min. So the driver should poll status in credit register to decide on driver timeout.
- In CvP initialization and update mode, when FPGA fabric is not programmed, the PCIe* features that uses FPGA fabric are not accessible.
- To generate the update image in the CvP update mode, you must use the same version of the Intel® Quartus® Prime software that you use to generate the base image.
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