# Load Quartus Prime Tcl Project package
package require ::quartus::project
package require ::quartus::flow

set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
	if {[string compare $quartus(project) "top"]} {
		puts "Project top is not open"
		set make_assignments 0
	}
} else {
	# Only open if not already open
	if {[project_exists top]} {
		project_open -revision top top
	} else {
		project_new -revision top top
	}
	set need_to_close_project 1
}

if {$make_assignments} {
	# Make general project assignments
	set_global_assignment -name FAMILY "Arria 10"
	set_global_assignment -name DEVICE 10AX115R3F40I2SGE2
	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
	set_location_assignment PIN_N13 -to clk
	set_instance_assignment -name IO_STANDARD LVDS -to clk
	set_location_assignment PIN_N12 -to "clk(n)"

	# Make initial assignments to create Signal Probe pins
	set_global_assignment -name CREATE_SIGNALPROBE_PIN wizard
	set_global_assignment -name CREATE_SIGNALPROBE_PIN probey
	set_location_assignment PIN_B25 -to wizard
	set_location_assignment PIN_G25 -to probey

	# If you want to compile the design manually,
	# you must save assignment changes to the QSF file
	# by calling "export_assignment"
	#export_assignments

	# Full compile
	execute_flow -compile

	# Perform debugging operations

	# Make assignments to connect nodes of interest to pins
	set_instance_assignment -name CONNECT_SIGNALPROBE_PIN wizard -to sprobe_me1
	set_instance_assignment -name CONNECT_SIGNALPROBE_PIN probey -to sprobe_me2
	export_assignments

	# Run the fitter with  --recompile to preserve timing
	# and quickly connect the Signal Probe pins
	execute_module -tool fit -args {--recompile}

	# Close project
	if {$need_to_close_project} {
	project_close
	}
}

//top.v
module top(
    input clk,
    input reset,
    output reg [7:0] bar,
    output wire aux_out
);

    reg sprobe_me1;
    reg sprobe_me2;
    
    always @(posedge clk) begin
        if(reset) begin
            sprobe_me1 <= 1'b0;
            sprobe_me2 <= 1'b0;
        end else begin
            sprobe_me1 <= bar[1] & bar[2];
            sprobe_me2 <= bar[7] ^ bar[5];
        end   
    end
    
    always @(posedge clk) begin
        if(reset) begin
            bar <= 8'b00000000;
        end else begin
            bar <= bar + 1'b1;
        end
    end
    
    wire sub_aux;
    sub sub_inst(.clk(clk), .reset(reset), .i1(bar[4]), .i2(bar[3]), .aux_out(sub_aux));
    
    assign aux_out = (sprobe_me1 | sprobe_me2) ^ (!sub_aux);

endmodule

module sub(
    input clk,
    input reset,
    input i1, i2,
    output wire aux_out,
    output wire sp1,
    output wire sp2
);
    reg sprobe_me1;
    reg sprobe_me2;
    
    always @(posedge clk) begin
        if(reset) begin
            sprobe_me1 <= 1'b1;
            sprobe_me2 <= 1'b0;
        end else begin
            sprobe_me1 <= i1 | i2;
            sprobe_me2 <= i1 ^ i2;
        end   
    end
    
    assign aux_out = sprobe_me1 & sprobe_me2;
    assign sp1 = sprobe_me1;
    assign sp2 = sprobe_me2;
    
endmodule