AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile

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ID 683757
Date 8/16/2018
Public
Document Table of Contents
Document Table of Contents x
AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile
AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile x
Setup Requirements Debug Flow with Signal Probe and Rapid Recompile Example of Using Signal Probe Routing Feature Document Revision History for AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile
Debug Flow with Signal Probe and Rapid Recompile x
Reserve Signal Probe Pins Compile the Design Assign Nodes to Signal Probe Pins Recompile the Design Check Connection Table in Fitter Report
Example of Using Signal Probe Routing Feature x
Example Files
AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile

AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile

Updated for:
Intel® Quartus® Prime Design Suite 18.0
This application note showcases a debugging technique that provides easy access to internal device signals without affecting the design.

Intel® Quartus® Prime Pro Edition Signal Probe feature allows you to route an internal node to a top-level I/O. When you start with a fully routed design, you can select and route signals for debugging to either previously reserved or currently unused I/O pins.

During Rapid Recompile, the Compiler reuses previous synthesis and fitting results whenever possible, and does not reprocess unchanged design blocks. When you make small design changes, using Rapid Recompile reduces timing variations and the total recompilation time.

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