1.4. Mailbox Client Intel® FPGA IP v20.1.2
|Intel® Quartus® Prime Version||Description||Impact|
|22.1||Updated response for CONFIG_STATUS command to include information on the configuration clock source.||Allows configuration of FPGA without a tile refclk present at time of configuration.|
|Enhanced the interrupt status register (ISR) and interrupt enable register (IER) to add protection for command/response and read/write FIFOs.|
|Removed mailbox command REBOOT_HPS as this command is unavailable for this IP.|
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