Mailbox Client Intel® FPGA IPs Release Notes

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ID 683754
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel® FPGA IP Release Notes
1. Mailbox Client Intel® FPGA IP Release Notes x
1.1. Mailbox Client Intel® FPGA IP 1.2. Agilex 5 Mailbox Client Intel® FPGA IP 1.3. Mailbox Client Intel FPGA IP User Guide Archives
1.1. Mailbox Client Intel® FPGA IP x
1.1.1. Mailbox Client Intel® FPGA IP v22.0.0 1.1.2. Mailbox Client Intel® FPGA IP v21.0.0 1.1.3. Mailbox Client Intel® FPGA IP v20.2.1 1.1.4. Mailbox Client Intel® FPGA IP v20.2.0 1.1.5. Mailbox Client Intel® FPGA IP v20.1.2 1.1.6. Mailbox Client Intel® FPGA IP v20.1.1 1.1.7. Mailbox Client Intel® FPGA IP v20.1.0 1.1.8. Mailbox Client Intel® FPGA IP v20.0.2 1.1.9. Mailbox Client Intel® FPGA IP v20.0.0 1.1.10. Mailbox Client Intel® FPGA IP v19.3 1.1.11. Intel FPGA Stratix 10 Mailbox Client v17.1
1.2. Agilex 5 Mailbox Client Intel® FPGA IP x
1.2.1. Agilex 5 Mailbox Client Intel® FPGA IP v1.0.0
1. Mailbox Client Intel® FPGA IP Release Notes

1.1.2. Mailbox Client Intel® FPGA IP v21.0.0

Table 2.  v21.0.0 2023.08.11
Quartus® Prime Version Description Impact
23.2 Added avmm_waitrequest signal to this IP. When migrating from Quartus® Prime software version 23.1 or earlier, you must regenerate the Mailbox Client Intel® FPGA IP to include this signal.
Added QSPI_SET_CS requirement after QSPI_OPEN command. When migrating from Quartus® Prime software version 23.1 or earlier, you must run QSPI_SET_CS after every QSPI_OPEN on Agilex™ devices.
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