Mailbox Client Intel® FPGA IP Release Notes

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ID 683754
Date 12/19/2022
Public
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1. Mailbox Client Intel® FPGA IP Release Notes
1. Mailbox Client Intel® FPGA IP Release Notes x
1.1. Mailbox Client Intel® FPGA IP v20.2.1 1.2. Mailbox Client Intel® FPGA IP v20.2.0 1.3. Mailbox Client Intel® FPGA IP v20.1.2 1.4. Mailbox Client Intel® FPGA IP v20.1.1 1.5. Mailbox Client Intel® FPGA IP v20.1.0 1.6. Mailbox Client Intel® FPGA IP v20.0.2 1.7. Mailbox Client Intel® FPGA IP v20.0.0 1.8. Mailbox Client Intel® FPGA IP v19.3 1.9. Intel FPGA Stratix 10 Mailbox Client v17.1 1.10. Mailbox Client Intel FPGA IP User Guide Archives
1. Mailbox Client Intel® FPGA IP Release Notes

1.6. Mailbox Client Intel® FPGA IP v20.0.2

Table 6.  v20.0.2 2021.03.29
Intel® Quartus® Prime Version Description Impact
21.1

Added support to reset Timer 1 and Timer 2 delay registers during the event of Mailbox Client Intel® FPGA IP reset assertion.

No impact in Timer 1 and Timer 2 registers usage in Intel® Quartus® Prime software version from 20.2 and 20.4.

You must regenerate the Mailbox Client Intel® FPGA IP when moving from Intel® Quartus® Prime software version 20.4 or earlier to Intel® Quartus® Prime software version 21.1.

Added support to enable the connection capability between Mailbox Client Intel® FPGA IP IRQ signal and Nios® II processor IRQ signal.

You must migrate to Intel® Quartus® Prime software version 21.1 and regenerate Mailbox Client Intel® FPGA IP to enable this feature.
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