Arria 10 Transceiver Native PHY IP Core Release Notes

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ID 683744
Date 10/31/2016
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1. Arria 10 Transceiver Native PHY IP Core Release Notes
1. Arria 10 Transceiver Native PHY IP Core Release Notes x
1.1. Arria 10 Transceiver Native PHY IP Core v15.1 Revision History 1.2. Arria 10 Transceiver Native PHY IP Core v15.0 Revision History 1.3. Arria 10 Transceiver Native PHY IP Core v14.1 Revision History 1.4. Arria 10 Transceiver Native PHY IP Core v14.0 Revision History 1.5. Arria 10 Transceiver Native PHY IP Core v13.1 Revision History
1. Arria 10 Transceiver Native PHY IP Core Release Notes

1.1. Arria 10 Transceiver Native PHY IP Core v15.1 Revision History

Table 1.  v15.1 November 2015
Description Impact

Issue: ACDS 15.1 introduces a necessary fix for Arria 10 transceiver designs. This fix introduces a change that affects post-fit simulation for designs containing Arria 10 Transceiver Native PHY, Arria 10 Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, and Arria 10 fPLL IP cores.

pll_powerdown is not connected for HSSI PLL IPs.

Workaround: Users requiring post-fit simulation of the transceiver PLLs in ACDS 15.1 need to disable the "Transceiver Reset Sequencer" for their design to produce a post-fit simulation netlist. However, this cannot and should not be used to produce the final bitstream for hardware. Hardware requires the "Transceiver Reset Sequencer" to be enabled.

To disable the "Transceiver Reset Sequencer" in the Quartus Prime software, add the following QSF to the Quartus Settings File for the project: 

set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS=1"

This will completely disable the reset sequencer in the design and restore the old behavior. This method does not allow post-fit simulation of the "Transceiver Reset Sequencer" logic.

Resolution: A modification to the PLL simulation models is planned for a subsequent release of ACDS 15.1 to remove the reset requirement.

pll_powerdown inputs to the Arria 10 Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, and Arria 10 fPLL IP cores for Quartus Prime synthesis. As a result, the resulting generated post-fit simulation will not have a reset input connection for the PLL and post-fit simulation will likely fail.

In Arria 10 devices, you may observe marginal core-to-periphery and periphery-to-core setup and hold violations (range: 80 ps - 100 ps) in transceiver based designs. You can ignore these violations in the 15.1 release. These setup and hold violations have no impact on hardware designs.
The Arria 10 Transceiver Native PHY IP core adds logic that controls and sequences the assertion and deassertion of the rx_analogreset and tx_analogreset signals internal to the core. The logic that performs this sequencing is inserted by the Quartus Prime software during synthesis. This change requires you to make one of two changes to your reset control logic that drives the rx_analogreset, tx_analogreset, and tx_digitalreset signals. Refer to the Resetting Transceiver Channels chapter of the Arria 10 Transceiver PHY User Guide for details about the new reset sequence requirements.
A new option in the Native PHY IP core called "Include PMA analog settings in configuration files" allows you to select whether you want analog settings and their dependent parameters to be part of your configuration files (MIF, SV, or H) for dynamic reconfiguration. If you select this option, a new tab opens up for you to select various analog settings. You must still use Quartus II Settings File (.qsf) assignments to specify the analog settings for their current configuration in the Quartus Prime software. This new GUI option does not remove the requirement to specify .qsf assignments for their analog settings. This option only allows you to include analog settings as part of the configuration files for reconfiguration.
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