Arria 10 Transceiver Native PHY IP Core Release Notes

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ID 683744
Date 10/31/2016
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Document Table of Contents x
1. Arria 10 Transceiver Native PHY IP Core Release Notes
1. Arria 10 Transceiver Native PHY IP Core Release Notes x
1.1. Arria 10 Transceiver Native PHY IP Core v15.1 Revision History 1.2. Arria 10 Transceiver Native PHY IP Core v15.0 Revision History 1.3. Arria 10 Transceiver Native PHY IP Core v14.1 Revision History 1.4. Arria 10 Transceiver Native PHY IP Core v14.0 Revision History 1.5. Arria 10 Transceiver Native PHY IP Core v13.1 Revision History
1. Arria 10 Transceiver Native PHY IP Core Release Notes

1.2. Arria 10 Transceiver Native PHY IP Core v15.0 Revision History

Table 2.  15.0 May 2015
Description Impact
Changed bit settings. You must upgrade any IPs generated prior to Quartus II software v15.0.

Added the following warning message to the GUI: "Enable dynamic reconfiguration should be enabled when Enable datapath and interface reconfiguration is enabled".

This message appears when dynamic reconfiguration is disabled while datapath reconfiguration is enabled.

-

Updated tooltips and added information messages for the parameters in the table below

Note: Information messages are displayed only if the parameter is enabled.
Table 3.  Tool Tip and Information Message Updates
Parameter Tool Tip Update Information Message
tx_pma_clkout Enables the optional tx_pma_clkout output clock. This is the parallel clock from the TX PMA. This port is not to be used to clock the data interface. The tx_pma_clkout port is not to be used to clock the data interface.
rx_pma_clkout Enables the optional rx_pma_clkout output clock. This is the recovered parallel clock from the RX CDR. This port is not to be used to clock the data interface. The rx_pma_clkout port is not to be used to clock the data interface.
tx_pma_div_clkout Enables the optional tx_pma_div_clkout output clock. This port should not be used for register mode data transfers. The tx_pma_div_clkout port should not be used for register mode data transfers.
rx_pma_div_clkout Enables the optional rx_pma_div_clkout output clock. This port should not be used for register mode data transfers. The rx_pma_div_clkout port should not be used for register mode data transfers.
-

Added the following information message to the GUI for tx_std_bitslipboundarysel: "The tx_std_bitslipboundarysel port must be enabled if Standard PCS TX bitslip capability is desired."

This message is displayed if TX bitslip is enabled and Std PCS is used.

-

Added warning messages for merging simplex IPs. The messages are displayed conditionally. For example, when embedded debug is enabled in a simplex design.

The following are example messages:

  • If this TX Simplex Native PHY instance needs to be merged with an RX Simplex Native PHY instance or a CDR PLL IP instance, ensure that reconfiguration inputs of both the PHY instances are driven by the same source.
  • If this RX Simplex Native PHY instance needs to be merged with an TX Simplex Native PHY instance, ensure that reconfiguration inputs of both the PHY instances are driven by the same source.
  • This TX Simplex Native PHY instance cannot be merged with an RX Simplex Native PHY instance or a CDR PLL IP instance.
  • This RX Simplex Native PHY instance cannot be merged with a TX Simplex Native PHY instance.
-

Removed the triggered option from the DFE adaptation mode parameter. If an IP core is generated before 15.0 with the triggered option selected for DFE adaptation mode, automatic upgrade maps triggered to continuous.

Also updated the tool tip for DFE adaptation mode accordingly. 		-

Added options to enable/disable the tx_pma_iqtxrx_clkout and rx_pma_iqtxrx_clkout ports. The ports are targeted for cascading the RX/TX PMA output clocks to the input of a PLL.

-

Fixed the issue where the following parameter values were not setting properly if using Riveria:

  • hssi_10g_tx_pcs_pseudo_seed_a
  • hssi_10g_tx_pcs_pseudo_seed_b
  • hssi_8g_rx_pcs_wa_pd_data
  • pma_tx_buf_xtx_path_pma_tx_divclk_hz
  • pma_rx_buf_xrx_path_pma_rx_divclk_hz
  • pma_tx_buf_xtx_path_tx_pll_clk_hz
-

When generating configuration files for RX-only configurations, the PHY incorrectly includes registers related to the TX CGB block.

When generating configuration files for TX-only configurations, the PHY incorrectly includes registers related to the RX PMA adaptation blocks.

The RX/TX configuration file inadvertently contains configuration data for the complimentary simplex direction. This causes an issue when a TX and RX PHY are merged to the same location because streaming the configuration data to one side affects the other.

Embedded streamer configurations are not affected as such and are not permitted in simplex configurations.

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