Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide

ID 683739
Date 11/06/2017
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3.1.3.1. Using Less Than 36-bit Operand In 18 × 18 Plus 36 Mode

This example shows how to configure the Cyclone® 10 GX Native Fixed Point DSP IP core to use 18 × 18 Plus 36 operational mode with a signed 12-bit input data of 101010101010 (binary) instead of a 36-bit operand.

  1. Set Representation format for bottom multiplier x operand: to signed.
  2. Set Representation format for bottom multiplier y operand: to unsigned.
  3. Set 'bx' input bus width to 18.
  4. Set 'by' input bus width to 18.
  5. Provide data of '111111111111111111' to bx input bus.
  6. Provide data of '111111101010101010' to by input bus.