Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide

ID 683739
Date 11/06/2017
Public

3.1.2. The 18 × 18 Sum of 2 Mode

In 18 × 18 Sum of 2 mode, the Cyclone® 10 GX Native Fixed Point DSP IP core enables the top and bottom multipliers and generates a result from addition or subtraction between the 2 multipliers. The sub dynamic control signal controls an adder to perform the addition or subtraction operations. The resulta output width of the Cyclone® 10 GX Native Fixed Point DSP IP core can support up to 64 bits when you enable accumulator/output cascade. This mode applies the equation of resulta =[±(ax * ay) + (bx * by)].

Figure 3. The 18 × 18 Sum of 2 Mode Architecture