Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide

ID 683739
Date 11/06/2017
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3.3. Clocking Scheme

The input, pipeline, and output registers in the Cyclone® 10 GX Native Fixed Point DSP IP core supports three clock sources/enables and two asynchronous clears. All input registers use aclr[0] and all pipeline and output registers use aclr[1]. Each register type can select one of the three clock sources and clock enable signals.

When you configure the Cyclone® 10 GX Native Fixed Point DSP IP core to 18 × 18 systolic operation mode, the Intel® Quartus® Prime software will set the input systolic register and the chainin systolic register clock source to the same clock source as the output register internally.

When you enable the double accumulator feature, the Intel® Quartus® Prime software will set the double accumulator register clock source to the same clock source as the output register internally.

Table 7.  Clocking Scheme Constraints

This tabe shows the constraints you must apply for all the registers clocking scheme.

Condition Constraint
When pre-adder is enabled Clock source for ay and az input registers must be the same.

Clock source for by and bz input registers must be the same.

When pipeline registers are enabled Clock source for all pipeline registers must be the same.
When any of the input registers for dynamic control signals Clock source for input registers for sub, accumulate, loadconst, and negate must be the same.