Native Loopback Accelerator Functional Unit User Guide for Intel FPGA Programmable Acceleration Card N3000

ID 683693
Date 11/25/2019
Public

2.2. The NLB Sample Accelerator Function (AF)

The Intel FPGA Programmable Acceleration Card N3000 platform package file includes the NLB sample AFU. The $N3000_PLATFORM_ROOT/rtl/pac_n3000_rtl_1.3.15/Factory/hw/afu/rtl/nlb_mode_0 directory stores source code for the following NLB sample AFU:
  • nlb_mode_0

The nlb_mode_0 works with hello_fpga sample application which resides here:

$N3000_PLATFORM_ROOT/samples/nlb0

The release package provides the following sample AF for the NLB sample AFU:
  • NLB mode 0 AF: requires hello_fpga or fpgabist utility to perform the read, write, and trupt tests.

The hello_fpga utilities help the appropriate AF to diagnose, test and report on the FPGA hardware.

Figure 1. Native Loopback (nlb_lpbk.sv) Top Level Wrapper

The following files implement the loopback function shown in the figure above:

Table 3.  NLB Files
File Name Description
nlb_lpbk.sv Top-level wrapper for NLB that instantiates the requestor and arbiter.
arbiter.sv Instantiates the test AF.
requestor.sv Accepts requests from the arbiter and formats the requests according to the CCI-P specification. Also implements flow control.
nlb_csr.sv Implements a 64-bit read/write Control and Status (CSR) registers. The registers support both 32- and 64-bit reads and writes.
nlb_gram_sdp.sv Implements a generic dual-port RAM with one write port and one read port.

NLB is a reference implementation of an AFU compatible with the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual. NLB’s primary function is to validate host connectivity using different memory access patterns. NLB also measures bandwidth and read/write latency.

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