Compiled Hardware Accelerator image implemented in FPGA logic that accelerates an application.
|AFU||Accelerator Functional Unit||Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance.|
|API||Application Programming Interface||A set of subroutine definitions, protocols, and tools for building software applications.|
|ASE||AFU Simulation Environment||
Co-simulation environment that allows you to use the same host application and AF in a simulation environment. ASE is part of the Intel® Acceleration Stack for FPGAs.
|CCI-P||Core Cache Interface||CCI-P is the standard interface AFUs use to communicate with the host.|
|CL||Cache Line||64-byte cache line|
|DFH||Device Feature Header||Creates a linked list of feature headers to provide an extensible way of adding features.|
|FIM||FPGA Interface Manager||
The FPGA hardware containing the FPGA Interface Unit (FIU) and external interfaces for memory, networking, etc.
The Accelerator Function (AF) interfaces with the FIM at run time.
|FIU||FPGA Interface Unit||
FIU is a platform interface layer that acts as a bridge between platform interfaces like PCIe* , UPI and AFU-side interfaces such as CCI-P.
|OPAE||Open Programmable Acceleration Engine||The OPAE is a software framework for managing and accessing AFs.|
|MPF||Memory Properties Factory||The MPF is a Basic Building Block (BBB) that AFUs can use to provide CCI-P traffic shaping operations for transactions with the FIU.|
|Msg||Message||Message - a control notification|
|NLB||Native Loopback||The NLB performs reads and writes to the CCI-P link to test connectivity and throughput.|
|RdLine_I||Read Line Invalid||Memory Read Request, with FPGA cache hint set to invalid. The line is not cached in the FPGA, but may cause FPGA cache pollution.
Note: The cache tag tracks the request status for all outstanding requests on Intel® Ultra Path Interconnect ( Intel® UPI). Therefore, even though RdLine_I is marked invalid upon completion, it consumes the cache tag temporarily to track the request status over UPI. This action may result in the eviction of a cache line, resulting in cache pollution. The advantage of using RdLine_I is that it is not tracked by CPU directory; thus it prevents snooping from CPU.
|RdLine-S||Read Line Shared||
Memory read request with FPGA cache hint set to shared. An attempt is made to keep it in the FPGA cache in a shared state.
|WrLine_I||Write Line Invalid||
Memory Write Request, with FPGA cache hint set to Invalid. The FIU writes the data with no intention of keeping the data in FPGA cache.
|WrLine_M||Write Line Modified||
Memory Write Request, with the FPGA cache hint set to Modified. The FIU writes the data and leaves it in the FPGA cache in a modified state.
Did you find the information on this page useful?