Native Loopback Accelerator Functional Unit User Guide for Intel FPGA Programmable Acceleration Card N3000

ID 683693
Date 11/25/2019
Public

2.4.1. NLB Mode0 Hello_FPGA Test Flow

  1. Software initializes Device Status Memory (DSM) to zero.
  2. Software writes the DSM BASE address to the AFU.

    CSR Write(DSM_BASE_H), CSRWrite(DSM_BASE_L)

  3. Software prepares source and destination memory buffer. This preparation is test specific.
  4. Software writes CSR_CTL[2:0]= 0x1. This write brings the test out of reset and into configuration mode. Configuration can proceed only when CSR_CTL[0]=1 & CSR_CTL[1]=1.
  5. Software configures the test parameters, such as src, destaddress, csr_cfg, num lines, and so on.
  6. Software CSR writes CSR_CTL[2:0]= 0x3. The AF begins test execution.
  7. Test completion:
    • Hardware completes when the test completes or detects an error. Upon completion, the hardware AF updates DSM_STATUS. Software polls DSM_STATUS[31:0]==1 to detect test completion.
    • Software can force test completion by writing CSR writes CSR_CTL[2:0]=0x7. Hardware AF updates DSM_STATUS.

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