Native Loopback Accelerator Functional Unit User Guide for Intel FPGA Programmable Acceleration Card N3000

ID 683693
Date 11/25/2019
Public

2.4. Test Modes

CSR_CFG[4:2] configures the test mode. The following four tests are available:
  • LPBK1: This is a memory copy test. The AF copies CSR_NUM_LINES from the source buffer to the destination buffer. Upon test completion, the software compares the source and destination buffers.
  • Read: This test stresses the read path and measures read bandwidth or latency. The AF reads CSR_NUM_LINES starting from the CSR_SRC_ADDR. This is only a bandwidth or latency test. It does not verify the data read.
  • Write: This test stresses the write path and measures write bandwidth or latency. The AF writes CSR_NUM_LINES starting from the CSR_SRC_ADDR. This is only a bandwidth or latency test. It does not verify the data written.
  • TRPUT: This test combines the reads and writes. It reads CSR_NUM_LINES starting from CSR_SRC_ADDR location and writes CSR_NUM_LINES to CSR_SRC_ADDR. It also measures read and write bandwidth. This test does not check the data. The reads and writes have no dependencies.

The following table shows the CSR_CFG encodings for the four tests. This table sets and CSR_NUM_LINES, <N>=14. You can change the number of cache lines by updating the CSR_NUM_LINES register.

Table 7.  Test Modes
Test Mode Encoding CSR_CFG[4:2] Cache Line Threshold CSR_NUM_LINES Cache Line Threshold for <N>=14
LPBK1 3'b000 2<N> 14'h3FFF
Read 3'b001 2<N> 14'h3FFF
Write 3'b010 2<N> 14'h3FFF
TRPUT 3'b011 2<N> 14'h3FFF

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