AN 837: Design Guidelines for HDMI Intel FPGA IP

ID 683677
Date 1/28/2019

1.3. Schematic Diagrams

The Bitec schematic diagrams in the provided links illustrate the topology for the Intel FPGA development boards.

Using HDMI 2.0 link topology requires you to meet the 3.3 V electrical compliance. To meet the 3.3 V compliance on Intel FPGA devices, you need to use a level shifter. Use a DC-coupled redriver or retimer as the level shifter for the transmitter and receiver.

The external vendor devices are TMDS181 and TDP158RSBT, both running on DC-coupled links. You need a proper pull-up at CEC lines to ensure functionality when inter-operating with other consumer remote control devices.

The Bitec schematic diagrams are CTS-certified. Certification is, however, product level specific. Platform designers are advised to certify the final product for proper functionality.