AN 837: Design Guidelines for HDMI Intel FPGA IP

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ID 683677
Date 1/28/2019
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for HDMI Intel® FPGA IP 2. Document Revision History for AN 837: Design Guidelines for HDMI Intel® FPGA IP
1. Design Guidelines for HDMI Intel® FPGA IP x
1.1. HDMI Intel® FPGA IP Design Guidelines 1.2. HDMI Intel® FPGA IP Board Design Tips 1.3. Schematic Diagrams 1.4. Hot-Plug Detect (HPD) 1.5. HDMI Intel® FPGA IP Display Data Channel (DDC)
1. Design Guidelines for HDMI Intel® FPGA IP
2. Document Revision History for AN 837: Design Guidelines for HDMI Intel® FPGA IP

1.5. HDMI Intel® FPGA IP Display Data Channel (DDC)

The HDMI Intel® FPGA IP DDC is based on the I2C signals (SCL and SDA) and require pull-up resistors.

To interface with an Intel FPGA, you need to translate the 5V SCL and SDA signal level to the FPGA I/O voltage level (VCCIO) using a voltage level translator, such as TI TXS0102 as used in the Bitec HDMI 2.0 daughter card. The TI TXS0102 voltage level translator device integrates internal pull-up resistors so that no on-board pull-up resistors are needed.

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