AN 837: Design Guidelines for HDMI Intel FPGA IP

ID 683677
Date 1/28/2019

1.5. HDMI Intel® FPGA IP Display Data Channel (DDC)

The HDMI Intel® FPGA IP DDC is based on the I2C signals (SCL and SDA) and require pull-up resistors.

To interface with an Intel FPGA, you need to translate the 5V SCL and SDA signal level to the FPGA I/O voltage level (VCCIO) using a voltage level translator, such as TI TXS0102 as used in the Bitec HDMI 2.0 daughter card. The TI TXS0102 voltage level translator device integrates internal pull-up resistors so that no on-board pull-up resistors are needed.