AN 837: Design Guidelines for HDMI Intel FPGA IP

ID 683677
Date 1/28/2019

1.1. HDMI Intel® FPGA IP Design Guidelines

The HDMI Intel® FPGA interface has Transition Minimized Differential Signaling (TMDS) data and clock channels. The interface also carries a Video Electronics Standards Association (VESA) Display Data Channel (DDC).

The TMDS channels carry video, audio, and auxiliary data. The DDC is based on I2C protocol. The HDMI Intel® FPGA IP core uses the DDC to read Extended Display Identification Data (EDID) and exchange configuration and status information between an HDMI source and sink.