Native Loopback Accelerator Functional Unit (AFU) User Guide

ID 683676
Date 8/05/2019

2.2. The NLB Sample Accelerator Function (AF)

The $OPAE_PLATFORM_ROOT/hw/samples directory stores source code for the following NLB sample AFUs:
  • nlb_mode_0
  • nlb_mode_0_stp
  • nlb_mode_3
Note: The $DCP_LOC/hw/samples directory stores the NLB sample AFUs source code for the 1.0 release package.
To understand the NLB sample AFU source code structure and how to build it, refer to one of the following Quick Start Guides (depending on which Intel FPGA PAC you are using):
  • If you are using Intel® PAC with Intel® Arria® 10 GX FPGA, refer to the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA.
  • If you are using Intel® FPGA PAC D5005, refer to the Intel Acceleration Stack Quick Start Guide for Intel FPGA Programmable Acceleration Card D5005.
The release package provides the following three sample AFs:
  • NLB mode 0 AF: requires hello_fpga or fpgadiag utility to perform the lpbk1 test.
  • NLB mode 3 AF: requires fpgadiag utility to perform the trupt, read, and write tests.
  • NLB mode 0 stp AF: requires hello_fpga or fpgadiag utility to perform the lpbak1 test.
    Note: The nlb_mode_0_stp is the same AFU as nlb_mode_0 but with Signal Tap debug feature enabled.

The fpgadiag and hello_fpga utilities help the appropriate AF to diagnose, test and report on the FPGA hardware.

Figure 1. Native Loopback ( Top Level Wrapper

The following files implement the loopback function shown in the figure above:

Table 4.  NLB Files
File Name Description Top-level wrapper for NLB that instantiates the requestor and arbiter. Instantiates the test AF. Accepts requests from the arbiter and formats the requests according to the CCI-P specification. Also implements flow control. Implements a 64-bit read/write Control and Status (CSR) registers. The registers support both 32- and 64-bit reads and writes. Implements a generic dual-port RAM with one write port and one read port.

NLB is a reference implementation of an AFU compatible with the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual. NLB’s primary function is to validate host connectivity using different memory access patterns. NLB also measures bandwidth and read/write latency. The bandwidth test has the following options:

  • 100% read
  • 100% write
  • 50% read and 50% writes