2.2. The NLB Sample Accelerator Function (AF)
- nlb_mode_0
- nlb_mode_0_stp
- nlb_mode_3
- If you are using Intel® PAC with Intel® Arria® 10 GX FPGA, refer to the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA.
- If you are using Intel® FPGA PAC D5005, refer to the Intel Acceleration Stack Quick Start Guide for Intel FPGA Programmable Acceleration Card D5005.
- NLB mode 0 AF: requires hello_fpga or fpgadiag utility to perform the lpbk1 test.
- NLB mode 3 AF: requires fpgadiag utility to perform the trupt, read, and write tests.
- NLB mode 0 stp AF: requires hello_fpga or fpgadiag utility to perform the lpbak1 test.
Note: The nlb_mode_0_stp is the same AFU as nlb_mode_0 but with Signal Tap debug feature enabled.
The fpgadiag and hello_fpga utilities help the appropriate AF to diagnose, test and report on the FPGA hardware.
The following files implement the loopback function shown in the figure above:
File Name | Description |
---|---|
nlb_lpbk.sv | Top-level wrapper for NLB that instantiates the requestor and arbiter. |
arbiter.sv | Instantiates the test AF. |
requestor.sv | Accepts requests from the arbiter and formats the requests according to the CCI-P specification. Also implements flow control. |
nlb_csr.sv | Implements a 64-bit read/write Control and Status (CSR) registers. The registers support both 32- and 64-bit reads and writes. |
nlb_gram_sdp.sv | Implements a generic dual-port RAM with one write port and one read port. |
NLB is a reference implementation of an AFU compatible with the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual. NLB’s primary function is to validate host connectivity using different memory access patterns. NLB also measures bandwidth and read/write latency. The bandwidth test has the following options:
- 100% read
- 100% write
- 50% read and 50% writes
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