Native Loopback Accelerator Functional Unit (AFU) User Guide

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ID 683676
Date 8/05/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. The Native Loopback Accelerator Functional Unit (AFU) 3. Document Revision History for the Native Loopback Accelerator Functional Unit (AFU) User Guide
1. About this Document x
1.1. Conventions 1.2. Acronyms 1.3. Acceleration Glossary
2. The Native Loopback Accelerator Functional Unit (AFU) x
2.1. Native Loopback (NLB) AFU Overview 2.2. The NLB Sample Accelerator Function (AF) 2.3. Native Loopback Control and Status Register Descriptions 2.4. Test Modes
2.4. Test Modes x
2.4.1. FPGA Diagnostics: fpgadiag 2.4.2. NLB Mode0 Hello_FPGA Test Flow
1. About this Document
2. The Native Loopback Accelerator Functional Unit (AFU)
3. Document Revision History for the Native Loopback Accelerator Functional Unit (AFU) User Guide

2.3. Native Loopback Control and Status Register Descriptions

Table 5.  CSR Names, Addresses and Descriptions
Byte Address (OPAE) Word Address (CCI-P) Access Name Width Description
0x0000 0x0000 RO DFH 64 AF Device Feature Header.
0x0008 0x0002 RO AFU_ID_L 64 AF ID low.
0x0010 0x0004 RO AFU_ID_H 64 AF ID high.
0x0018 0x0006 Rsvd CSR_DFH_RSVD0 64 Mandatory Reserved 0.
0x0020 0x0008 RO CSR_DFH_RSVD1 64 Mandatory Reserved 1.
0x0100 0x0040 RW CSR_SCRATCHPAD0 64 Scratchpad register 0.
0x0108 0x0042 RW CSR_SCRATCHPAD1 64 Scratchpad register 2.
0x0110 0x0044 RW CSR_AFU_DSM_BASEL 32 Lower 32-bits of AF DSM base address. The lower 6 bits are 4x00 because the address is aligned to the 64-byte cache line size.
0x0114 0x0045 RW CSR_AFU_DSM_BASEH 32 Upper 32-bits of AF DSM base address.
0x0120 0x0048 RW CSR_SRC_ADDR 64 Start physical address for source buffer. All read requests target this region.
0x0128 0x004A RW CSR_DST_ADDR 64 Start physical address for destination buffer. All write requests target this region
0x0130 0x004C RW CSR_NUM_LINES 32 Number of cache lines.

0x0138

0x004E

RW

CSR_CTL

32

 Controls test flow, start, stop, force completion.
0x0140 0x0050 RW CSR_CFG 32 Configures test parameters.
0x0148 0x0052 RW CSR_INACT_THRESH 32 Inactivity threshold limit.
0x0150 0x0054 RW CSR_INTERRUPT0 32 SW allocates Interrupt APIC ID and Vector to device.
DSM Offset Map
0x0040 0x0010 RO DSM_STATUS 32 Test status and error register.
Table 6.  CSR Bit Fields with ExamplesThis table lists the CSR bit fields that depend on the value of the CSR_NUM_LINES, <N>. In the example below <N> = 14.
Name Bit Field Access Description
CSR_SRC_ADDR [63:<N>] RW 2^(N+6)MB aligned address points to the start of the read buffer.
[<N>-1:0] RW 0x0.
CSR_DST_ADDR [63:<N>] RW 2^(N+6)MB aligned address points to the start of the write buffer.
[<N>-1:0] RW 0x0.
CSR_NUM_LINES [31:<N>] RW 0x0.
[<N>-1:0] RW

Number of cache lines to read or write. This threshold may be different for each test AF.

Note:

Ensure that source and destination buffers are large enough to accommodate the <N> cache lines.

CSR_NUM_LINES should be less than or equal to <N>.

For the following values, assume <N>=14. Then, CSR_SRC_ADDR and CSR_DST_ADDR accept 2^20 (0x100000).

CSR_SRC_ADDR [31:14] RW 1MB aligned address.
[13:0] RW 0x0.
CSR_DST_ADDR [31:14] RW 1MB aligned address.
[13:0] RW 0x0.
CSR_NUM_LINES [31:14] RW 0x0.
[13:0] RW

Number of cache lines to read or write. This threshold may be different for each test AF.

Note: Ensure that source and destination buffers are large enough to accommodate the <N> cache lines.
Table 7.  Additional CSR Bit Fields
Name Bit Field Access Description
CSR_CTL [31:3] RW Reserved.
[2] RW Force test completion. Writes test completion flag and other performance counters to csr_stat. After forcing test completion, the hardware state is identical to a non-forced test completion.
[1] RW Starts test execution.
[0] RW Active low test reset. When low, all configuration parameters change to their default values.
CSR_CFG [29] RW cr_interrupt_testmode tests interrupts. Generates an interrupt at the end of each test.

[28]

RW

 cr_interrupt_on_error sends an interrupt when upon error detection.
[27:20] RW

cr_test_cfg configures the behavior of each test mode.

[13:12] RW cr_chsel selects the virtual channel.

[10:9]

RW

cr_rdsel configures the read request type. The encodings have the following valid values:

  • 1'b00: RdLine_S
  • 2'b01: RdLine_I
  • 2'b11: Mixed mode
[8] RW

cr_delay_en enables random delay insertion between requests.

[6:5] RW Configures test mode,cr_multiCL-len. Valid values are 0,1,and 3.
[4:2] RW cr_mode, configures test mode. The following values are valid:
  • 3'b000: LPBK1
  • 3'b001: Read
  • 3'b010: Write
  • 3'b011: TRPUT

For more information about the test mode, refer to the Test Modes topic below.

[1] RW

c_cont selects test rollover or test termination.

  • When 1'b0, the test terminates. Updates the status CSR when CSR_NUM_LINES count is reached.

  • When 1'b1, the test rolls over to the start address after it reaches the CSR_NUM_LINES count. In rollover mode, the test terminates only upon error.

[0] RW

cr_wrthru_en switches between WrLine_I and Wrline_M request types.

  • 1'b0: WrLine_M
  • 1'b1: WrLine_I
CSR_INACT_THRESHOLD [31:0] RW

Inactivity threshold limit. Detects the duration of stalls during a test run. Counts the number of consecutive idle cycles. If the inactivity count > CSR_INACT_THRESHOLD, no requests are sent, no responses are received, and the inact_timeout signal is set.

Writing 1 to CSR_CTL[1] activates this counter.

CSR_INTERRUPT0 [23:16] RW The Interrupt Vector Number for the device.
[15:0] RW apic_id is the APIC OD for the device.
DSM_STATUS [511:256] RO Error dump form Test Mode.
[255:224] RO End Overhead.
[223:192] RO Start Overhead.
[191:160] RO Number of Writes.
[159:128] RO Number of Reads.
[127:64] RO Number of Clocks.
[63:32] RO Test error register.
[31:16] RO Compare and exchange success counter.
[15:1] RO Unique ID for each DSM status write.
[0] RO Test completion flag.
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