Visible to Intel only — GUID: sss1440053905885
Ixiasoft
Visible to Intel only — GUID: sss1440053905885
Ixiasoft
3.3. JTAG Configuration
JTAG-chain device programming is ideal during development. JTAG-chain device configuration uses the JTAG pins to configure the Intel Agilex® 7 FPGA directly with the .sof/.rbf file. Configuration using the JTAG device chain allows faster development because it does not require you to program external flash memory. You can also use JTAG to reprogram if the image stored in quad SPI memory. You can also use the JTAG configuration scheme to reprogram the quad SPI memory if the quad SPI content is corrupted or invalid.
The Intel® Quartus® Prime software generates a .sof/.rbf file containing the FPGA design information. You can use the .sof/.rbf file with a JTAG programmer to configure the Intel Agilex® 7 device. The Intel® FPGA Download Cable II and the Intel® FPGA Ethernet Cable both can support the VCCIO_SDM supply at 1.8 V. Alternatively, you can use the Jam* STAPL Format File (.jam) or Jam* Byte Code File (.jbc) for JTAG configuration. After the JTAG configuration, the host executes CONFIG_STATUS SDM command to ensure the configuration is successful.
Intel Agilex® 7 devices automatically compress the configuration bitstream. You cannot disable compression in Intel Agilex® 7 devices.
Mode | Data Width (bits) | Max Clock Rate | Max Data Rate | MSEL[2:0] | |
---|---|---|---|---|---|
Passive | JTAG | 1 | 30 MHz | 30 Mbps | 3'b111 |
Configuration Function | Pin Type | Direction | Powered by |
---|---|---|---|
TCK | Fixed | Input | VCCIO_SDM |
TDI 13 | Fixed | Input | VCCIO_SDM |
TMS 13 | Fixed | Input | VCCIO_SDM |
TDO 13 | Fixed | Output | VCCIO_SDM |
nSTATUS | SDM I/O | Output | VCCIO_SDM |
nCONFIG | SDM I/O | Input | VCCIO_SDM |
MSEL[2:0] | SDM I/O | Input | VCCIO_SDM |
Section Content
JTAG Configuration Scheme Hardware Components and File Types
JTAG Device Configuration
JTAG Multi-Device Configuration
Debugging Guidelines for the JTAG Configuration Scheme